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feat: add displays info (#1052)

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* test

* feat: dp info on amd

* chore: add other display types

* feat: use libdisplay-info, add screen size

* feat: add GUI

* feat: WIP nvidia

* feat: reuse display handle

* chore: clippy fixes

* chore: cleanup

* chore: make display-info an optional feature, add build dependency

* fix: ci

* fix ui imports

* fix: add new dependency to flatpak

* fix: add hwdata flatpak module
This commit is contained in:
Ilya Zlobintsev
2026-06-19 22:22:03 +03:00
committed by GitHub
parent 6c4e27d1d8
commit e2caa24ca8
39 changed files with 13648 additions and 90 deletions
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lact-daemon/include/nvidia.h
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#include "nvidia/kernel-open/common/inc/nv-ioctl-numbers.h"
#include "nvidia/nvapi/nvapi_lite_common.h"
#include "nvidia/src/common/sdk/nvidia/inc/class/cl0073.h"
#include "nvidia/src/common/sdk/nvidia/inc/class/cl0080.h"
#include "nvidia/src/common/sdk/nvidia/inc/class/cl2080.h"
#include "nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h"
#include "nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h"
#include "nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h"
#include "nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h"
#include "nvidia/src/common/sdk/nvidia/inc/nvos.h"
#include "nvidia/src/nvidia/arch/nvalloc/unix/include/nv_escape.h"
#include "nvidia/src/nvidia/arch/nvalloc/unix/include/nv_escape.h"
#include <stdint.h>
#include "nvidia/kernel-open/nvidia-drm/nv_drm_common_ioctl.h"
lact-daemon/include/nvidia/kernel-open/nvidia-drm/nv_drm_common_ioctl.h
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+586
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@@ -0,0 +1,586 @@
/*
* Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _NV_DRM_COMMON_IOCTL_H_
#define _NV_DRM_COMMON_IOCTL_H_
#include <drm/drm.h>
/*
* We should do our best to keep these values constant. Any change to these will
* be backwards incompatible with client applications that might be using them
*/
#define DRM_NVIDIA_GET_CRTC_CRC32 0x00
#define DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY 0x01
#define DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY 0x02
#define DRM_NVIDIA_GET_DEV_INFO 0x03
#define DRM_NVIDIA_FENCE_SUPPORTED 0x04
#define DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE 0x05
#define DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH 0x06
#define DRM_NVIDIA_GET_CLIENT_CAPABILITY 0x08
#define DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY 0x09
#define DRM_NVIDIA_GEM_MAP_OFFSET 0x0a
#define DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY 0x0b
#define DRM_NVIDIA_GET_CRTC_CRC32_V2 0x0c
#define DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY 0x0d
#define DRM_NVIDIA_GEM_IDENTIFY_OBJECT 0x0e
#define DRM_NVIDIA_DMABUF_SUPPORTED 0x0f
#define DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID 0x10
#define DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID 0x11
#define DRM_NVIDIA_GRANT_PERMISSIONS 0x12
#define DRM_NVIDIA_REVOKE_PERMISSIONS 0x13
#define DRM_NVIDIA_SEMSURF_FENCE_CTX_CREATE 0x14
#define DRM_NVIDIA_SEMSURF_FENCE_CREATE 0x15
#define DRM_NVIDIA_SEMSURF_FENCE_WAIT 0x16
#define DRM_NVIDIA_SEMSURF_FENCE_ATTACH 0x17
#define DRM_NVIDIA_GET_DRM_FILE_UNIQUE_ID 0x18
#define DRM_NVIDIA_REGISTER_ROI 0x19 /* Register ROI */
#define DRM_NVIDIA_UNREGISTER_ROI 0x1a /* Unregister ROI */
#define DRM_NVIDIA_GET_CRTC_ROI_CRCS 0x1b /* Read CRCs for registered ROIs */
#define DRM_NVIDIA_GET_ROI_CAPABILITIES 0x1c /* Get ROI related capabilities */
/* Maximum possible telltale CRCs per plane (used for array size)
* actual value is queried from the plane property NV_DRM_NUM_PLANE_TELLTALE_CRCS*/
#define NV_DRM_MAX_TELLTALES_PER_PLANE 64
/* Maximum possible ROIs per CRTC (used for array size)
* actual value is queried from DRM_NVIDIA_GET_ROI_CAPABILITIES */
#define NV_DRM_MAX_ROIS_PER_CRTC 64
/* IOCTLs */
#define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY), \
struct drm_nvidia_gem_import_nvkms_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY), \
struct drm_nvidia_gem_import_userspace_memory_params)
#define DRM_IOCTL_NVIDIA_GET_DEV_INFO \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DEV_INFO), \
struct drm_nvidia_get_dev_info_params)
/*
* XXX Solaris compiler has issues with DRM_IO. None of this is supported on
* Solaris anyway, so just skip it.
*
* 'warning: suggest parentheses around arithmetic in operand of |'
*/
#if defined(NV_LINUX) || defined(NV_BSD)
#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED \
DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED)
#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED \
DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_DMABUF_SUPPORTED)
#else
#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED 0
#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED 0
#endif
#define DRM_IOCTL_NVIDIA_PRIME_FENCE_CONTEXT_CREATE \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE),\
struct drm_nvidia_prime_fence_context_create_params)
#define DRM_IOCTL_NVIDIA_GEM_PRIME_FENCE_ATTACH \
DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH), \
struct drm_nvidia_gem_prime_fence_attach_params)
#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \
struct drm_nvidia_get_client_capability_params)
#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \
struct drm_nvidia_get_crtc_crc32_params)
#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \
struct drm_nvidia_get_crtc_crc32_v2_params)
#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \
struct drm_nvidia_gem_export_nvkms_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \
struct drm_nvidia_gem_map_offset_params)
#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \
struct drm_nvidia_gem_alloc_nvkms_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \
struct drm_nvidia_gem_export_dmabuf_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \
struct drm_nvidia_gem_identify_object_params)
#define DRM_IOCTL_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID),\
struct drm_nvidia_get_dpy_id_for_connector_id_params)
#define DRM_IOCTL_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID),\
struct drm_nvidia_get_connector_id_for_dpy_id_params)
#define DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GRANT_PERMISSIONS), \
struct drm_nvidia_grant_permissions_params)
#define DRM_IOCTL_NVIDIA_REVOKE_PERMISSIONS \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_REVOKE_PERMISSIONS), \
struct drm_nvidia_revoke_permissions_params)
#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_CTX_CREATE \
DRM_IOWR((DRM_COMMAND_BASE + \
DRM_NVIDIA_SEMSURF_FENCE_CTX_CREATE), \
struct drm_nvidia_semsurf_fence_ctx_create_params)
#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_CREATE \
DRM_IOWR((DRM_COMMAND_BASE + \
DRM_NVIDIA_SEMSURF_FENCE_CREATE), \
struct drm_nvidia_semsurf_fence_create_params)
#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_WAIT \
DRM_IOW((DRM_COMMAND_BASE + \
DRM_NVIDIA_SEMSURF_FENCE_WAIT), \
struct drm_nvidia_semsurf_fence_wait_params)
#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_ATTACH \
DRM_IOW((DRM_COMMAND_BASE + \
DRM_NVIDIA_SEMSURF_FENCE_ATTACH), \
struct drm_nvidia_semsurf_fence_attach_params)
#define DRM_IOCTL_NVIDIA_GET_DRM_FILE_UNIQUE_ID \
DRM_IOWR((DRM_COMMAND_BASE + \
DRM_NVIDIA_GET_DRM_FILE_UNIQUE_ID), \
struct drm_nvidia_get_drm_file_unique_id_params)
#define DRM_IOCTL_NVIDIA_REGISTER_ROI \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_REGISTER_ROI), \
struct drm_nvidia_register_roi_params)
#define DRM_IOCTL_NVIDIA_UNREGISTER_ROI \
DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_UNREGISTER_ROI), \
struct drm_nvidia_unregister_roi_params)
#define DRM_IOCTL_NVIDIA_GET_CRTC_ROI_CRCS \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_ROI_CRCS), \
struct drm_nvidia_read_crc_params)
#define DRM_IOCTL_NVIDIA_GET_ROI_CAPABILITIES \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_ROI_CAPABILITIES), \
struct drm_nvidia_get_roi_capabilities_params)
struct drm_nvidia_gem_import_nvkms_memory_params {
uint64_t mem_size; /* IN */
uint64_t nvkms_params_ptr; /* IN */
uint64_t nvkms_params_size; /* IN */
uint32_t handle; /* OUT */
uint32_t __pad;
};
struct drm_nvidia_gem_import_userspace_memory_params {
uint64_t size; /* IN Size of memory in bytes */
uint64_t address; /* IN Virtual address of userspace memory */
uint32_t handle; /* OUT Handle to gem object */
};
struct drm_nvidia_get_dev_info_params {
uint32_t gpu_id; /* OUT */
uint32_t mig_device; /* OUT */
uint32_t primary_index; /* OUT; the "card%d" value */
uint32_t supports_alloc; /* OUT */
/* The generic_page_kind, page_kind_generation, and sector_layout
* fields are only valid if supports_alloc is true.
* See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these. */
uint32_t generic_page_kind; /* OUT */
uint32_t page_kind_generation; /* OUT */
uint32_t sector_layout; /* OUT */
uint32_t supports_sync_fd; /* OUT */
uint32_t supports_semsurf; /* OUT */
};
struct drm_nvidia_prime_fence_context_create_params {
uint32_t handle; /* OUT GEM handle to fence context */
uint32_t index; /* IN Index of semaphore to use for fencing */
uint64_t size; /* IN Size of semaphore surface in bytes */
/* Params for importing userspace semaphore surface */
uint64_t import_mem_nvkms_params_ptr; /* IN */
uint64_t import_mem_nvkms_params_size; /* IN */
/* Params for creating software signaling event */
uint64_t event_nvkms_params_ptr; /* IN */
uint64_t event_nvkms_params_size; /* IN */
};
struct drm_nvidia_gem_prime_fence_attach_params {
uint32_t handle; /* IN GEM handle to attach fence to */
uint32_t fence_context_handle; /* IN GEM handle to fence context on which fence is run on */
uint32_t sem_thresh; /* IN Semaphore value to reach before signal */
uint32_t __pad;
};
struct drm_nvidia_get_client_capability_params {
uint64_t capability; /* IN Client capability enum */
uint64_t value; /* OUT Client capability value */
};
/* Struct that stores Crc value and if it is supported by hardware */
struct drm_nvidia_crtc_crc32 {
uint32_t value; /* Read value, undefined if supported is false */
uint8_t supported; /* Supported boolean, true if readable by hardware */
uint8_t __pad0;
uint16_t __pad1;
};
struct drm_nvidia_crtc_crc32_v2_out {
struct drm_nvidia_crtc_crc32 compositorCrc32; /* OUT compositor hardware CRC32 value */
struct drm_nvidia_crtc_crc32 rasterGeneratorCrc32; /* OUT raster generator CRC32 value */
struct drm_nvidia_crtc_crc32 outputCrc32; /* OUT SF/SOR CRC32 value */
};
struct drm_nvidia_get_crtc_crc32_v2_params {
uint32_t crtc_id; /* IN CRTC identifier */
struct drm_nvidia_crtc_crc32_v2_out crc32; /* OUT Crc32 output structure */
};
struct drm_nvidia_get_crtc_crc32_params {
uint32_t crtc_id; /* IN CRTC identifier */
uint32_t crc32; /* OUT CRC32 value */
};
struct drm_nvidia_gem_export_nvkms_memory_params {
uint32_t handle; /* IN */
uint32_t __pad;
uint64_t nvkms_params_ptr; /* IN */
uint64_t nvkms_params_size; /* IN */
};
struct drm_nvidia_gem_map_offset_params {
uint32_t handle; /* IN Handle to gem object */
uint32_t __pad;
uint64_t offset; /* OUT Fake offset */
};
#define NV_GEM_ALLOC_NO_SCANOUT (1 << 0)
struct drm_nvidia_gem_alloc_nvkms_memory_params {
uint32_t handle; /* OUT */
uint8_t block_linear; /* IN */
uint8_t compressible; /* IN/OUT */
uint16_t __pad0;
uint64_t memory_size; /* IN */
uint32_t flags; /* IN */
uint32_t __pad1;
};
struct drm_nvidia_gem_export_dmabuf_memory_params {
uint32_t handle; /* IN GEM Handle*/
uint32_t __pad;
uint64_t nvkms_params_ptr; /* IN */
uint64_t nvkms_params_size; /* IN */
};
typedef enum {
NV_GEM_OBJECT_NVKMS,
NV_GEM_OBJECT_DMABUF,
NV_GEM_OBJECT_USERMEMORY,
NV_GEM_OBJECT_UNKNOWN = 0x7fffffff /* Force size of 32-bits. */
} drm_nvidia_gem_object_type;
struct drm_nvidia_gem_identify_object_params {
uint32_t handle; /* IN GEM handle*/
drm_nvidia_gem_object_type object_type; /* OUT GEM object type */
};
struct drm_nvidia_get_dpy_id_for_connector_id_params {
uint32_t connectorId; /* IN */
uint32_t dpyId; /* OUT */
};
struct drm_nvidia_get_connector_id_for_dpy_id_params {
uint32_t dpyId; /* IN */
uint32_t connectorId; /* OUT */
};
enum drm_nvidia_permissions_type {
NV_DRM_PERMISSIONS_TYPE_MODESET = 2,
NV_DRM_PERMISSIONS_TYPE_SUB_OWNER = 3
};
struct drm_nvidia_grant_permissions_params {
int32_t fd; /* IN */
uint32_t dpyId; /* IN */
uint32_t type; /* IN */
};
struct drm_nvidia_revoke_permissions_params {
uint32_t dpyId; /* IN */
uint32_t type; /* IN */
};
struct drm_nvidia_semsurf_fence_ctx_create_params {
uint64_t index; /* IN Index of the desired semaphore in the
* fence context's semaphore surface */
/* Params for importing userspace semaphore surface */
uint64_t nvkms_params_ptr; /* IN */
uint64_t nvkms_params_size; /* IN */
uint32_t handle; /* OUT GEM handle to fence context */
uint32_t __pad;
};
struct drm_nvidia_semsurf_fence_create_params {
uint32_t fence_context_handle; /* IN GEM handle to fence context on which
* fence is run on */
uint32_t timeout_value_ms; /* IN Timeout value in ms for the fence
* after which the fence will be signaled
* with its error status set to -ETIMEDOUT.
* Default timeout value is 5000ms */
uint64_t wait_value; /* IN Semaphore value to reach before signal */
int32_t fd; /* OUT sync FD object representing the
* semaphore at the specified index reaching
* a value >= wait_value */
uint32_t __pad;
};
/*
* Note there is no provision for timeouts in this ioctl. The kernel
* documentation asserts timeouts should be handled by fence producers, and
* that waiters should not second-guess their logic, as it is producers rather
* than consumers that have better information when it comes to determining a
* reasonable timeout for a given workload.
*/
struct drm_nvidia_semsurf_fence_wait_params {
uint32_t fence_context_handle; /* IN GEM handle to fence context which will
* be used to wait on the sync FD. Need not
* be the fence context used to create the
* sync FD. */
int32_t fd; /* IN sync FD object to wait on */
uint64_t pre_wait_value; /* IN Wait for the semaphore represented by
* fence_context to reach this value before
* waiting for the sync file. */
uint64_t post_wait_value; /* IN Signal the semaphore represented by
* fence_context to this value after waiting
* for the sync file */
};
struct drm_nvidia_semsurf_fence_attach_params {
uint32_t handle; /* IN GEM handle of buffer */
uint32_t fence_context_handle; /* IN GEM handle of fence context */
uint32_t timeout_value_ms; /* IN Timeout value in ms for the fence
* after which the fence will be signaled
* with its error status set to -ETIMEDOUT.
* Default timeout value is 5000ms */
uint32_t shared; /* IN If true, fence will reserve shared
* access to the buffer, otherwise it will
* reserve exclusive access */
uint64_t wait_value; /* IN Semaphore value to reach before signal */
};
struct drm_nvidia_get_drm_file_unique_id_params {
uint64_t id; /* OUT Unique ID of the DRM file */
};
/**
* @brief Parameters for getting ROI capabilities
*
* This structure is used with the DRM_NVIDIA_GET_ROI_CAPABILITIES ioctl to
* get ROI related capabilities.
*
* @param[out] max_rois Maximum number of ROIs that can be registered
*/
struct drm_nvidia_get_roi_capabilities_params {
uint32_t max_registered_rois; /* OUT Maximum number of ROIs that can be registered */
uint32_t reserved[7];
};
/**
* @brief Rectangle structure for ROI
*
* This structure is used to define a rectangle region of interest.
*
* @param[in] x X coordinate of the top-left corner
* @param[in] y Y coordinate of the top-left corner
* @param[in] width Width of the ROI
* @param[in] height Height of the ROI
*/
struct drm_nvidia_roi_rect {
uint32_t x;
uint32_t y;
uint32_t width;
uint32_t height;
};
/**
* @brief Parameters for registering a Region of Interest (ROI)
*
* This structure is used to register an ROI region in the Region RAM which can
* then be referenced by its region handle when configuring a window to enable CRC.
* The region handle is treated as a separate resource and must be registered
* outside of the regular commit cycle.
*
* @param[in] rect Rectangle defining the ROI coordinates
* @param[out] region_handle Unique handle for the registered ROI
*/
struct drm_nvidia_register_roi_params {
struct drm_nvidia_roi_rect rect; /* IN */
uint64_t region_handle; /* OUT */
};
/**
* @brief Parameters for unregistering a Region of Interest (ROI)
*
* This structure is used to unregister a previously registered ROI region.
* Note: A region handle that is actively in use (configured in the CRC enablement
* property) cannot be unregistered. Only a handle that was previously registered
* by this client can be unregistered.
*
* @param[in] region_handle Handle of the ROI to unregister
*/
struct drm_nvidia_unregister_roi_params {
uint64_t region_handle; /* IN */
};
/**
* @brief Per-plane telltale CRC configuration
*
* This structure defines the configuration for telltale CRC on a per-plane basis.
* Each plane can have multiple telltale CRC regions configured, with each region
* referencing a previously registered ROI via its region handle.
*
* @param[in] region_handle Handle of registered ROI to use
* @param[in] golden_crc Expected CRC value for safety interrupts (0 if not configured)
*/
struct drm_nvidia_telltale_per_plane_config {
uint64_t region_handle; /* IN */
uint64_t golden_crc; /* IN */
};
/* NV_DRM_NUM_PLANE_TELLTALE_CRCS is a plane property that can be read to get
* the max number of telltale CRCs that can be enabled on a plane */
/**
* @brief Blob property structure for NV_DRM_PLANE_TELLTALES
*
* This structure is used as the content for the NV_DRM_PLANE_TELLTALES blob property
* that is set on a plane before atomic commit. It contains an array of telltale
* configurations, one for each telltale CRC region that should be enabled on the plane.
* The number of configurations should not exceed the value read from the
* NV_DRM_NUM_PLANE_TELLTALE_CRCS plane property.
* This property is expected to be set in the regular atomic commit operation.
*
* @param[in] telltale_configs Array of telltale CRC configurations
*/
struct drm_nvidia_plane_telltales {
struct drm_nvidia_telltale_per_plane_config \
telltale_configs[NV_DRM_MAX_TELLTALES_PER_PLANE]; /* IN */
};
/**
* @brief ROI CRC data structure
*
* This structure contains the CRC value for a specific ROI region. It is used
* as part of the array returned by the DRM_NVIDIA_GET_CRTC_ROI_CRCS ioctl to
* provide CRC values for all active ROI regions on a CRTC.
*
* @param[out] region_handle Handle of the ROI region
* @param[out] crc Computed CRC value for this ROI
* @param[in/out] reserved Reserved fields for future use
*/
struct drm_nvidia_roi_crc {
uint64_t region_handle; /* OUT */
uint64_t crc; /* OUT */
uint64_t reserved[4];
};
/**
* @brief Parameters for reading CRC data from CRTC
*
* This structure is used with the DRM_NVIDIA_GET_CRTC_ROI_CRCS ioctl to read
* the CRC values for all registered ROI regions that are currently active on
* the specified CRTC. The ioctl will populate the roi_crcs array with CRC data
* for each active region and set num_collected_crcs to indicate how many valid
* entries are in the array.
* Please note that only the last collected CRC is returned per active region handle.
*
* @param[in] crtc_id CRTC identifier to read CRCs from
* @param[out] num_collected_crcs Number of valid CRC entries returned
* @param[in/out] reserved Reserved fields for future use
* @param[out] roi_crcs Array of ROI CRC data
*/
struct drm_nvidia_read_crc_params {
int32_t crtc_id; /* IN */
int32_t num_collected_crcs; /* OUT */
struct drm_nvidia_roi_crc roi_crcs[NV_DRM_MAX_ROIS_PER_CRTC]; /* OUT */
uint64_t reserved[4];
};
/**
* @brief Named transfer function enum
*
* This enum defines the named transfer functions that can be used to set
* the degamma and regamma transfer functions properties.
*/
enum nv_drm_transfer_function {
NV_DRM_TRANSFER_FUNCTION_DEFAULT,
NV_DRM_TRANSFER_FUNCTION_LINEAR,
NV_DRM_TRANSFER_FUNCTION_PQ,
/*
* nvidia-drm only supports the transfer function types defined above. The
* below transfer functions are currently only supported by tegradisp-drm,
* and not by nvidia-drm. Do not define a transfer function above
* NV_DRM_TRANSFER_FUNCTION_SRGB without updating
* NV_DRM_TRANSFER_FUNCTION_MAX.
*/
NV_DRM_TRANSFER_FUNCTION_SRGB,
NV_DRM_TRANSFER_FUNCTION_SMPTE_170M,
NV_DRM_TRANSFER_FUNCTION_TEGRA_MAX,
NV_DRM_TRANSFER_FUNCTION_MAX = NV_DRM_TRANSFER_FUNCTION_SRGB,
};
#endif /* _NV_DRM_COMMON_IOCTL_H_ */
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/class/cl0073.h
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/*
* Copyright (c) 2001-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0073_h_
#define _cl0073_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV04_DISPLAY_COMMON (0x00000073)
/* event values */
#define NV0073_NOTIFIERS_SW (0)
#define NV0073_NOTIFIERS_LTM_CALC_TIMEOUT (5)
#define NV0073_NOTIFIERS_MAXCOUNT (6)
#define NV0073_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV0073_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV0073_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV0073_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV0073_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
/* pio method data structure */
typedef volatile struct _cl0073_tag0 {
NvV32 Reserved00[0x7c0];
} Nv073Typedef, Nv04DisplayCommon;
#define NV073_TYPEDEF Nv04DisplayCommon
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0073_h_ */
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
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/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV04_DISPLAY_COMMON control commands and parameters */
#define NV0073_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0073, NV0073_CTRL_##cat, idx)
/* NV04_DISPLAY_COMMON command categories (6bits) */
#define NV0073_CTRL_RESERVED (0x00U)
#define NV0073_CTRL_SYSTEM (0x01U)
#define NV0073_CTRL_SPECIFIC (0x02U)
#define NV0073_CTRL_EVENT (0x03U)
#define NV0073_CTRL_INTERNAL (0x04U)
#define NV0073_CTRL_COMMON (0x05U)
#define NV0073_CTRL_DFP (0x11U)
#define NV0073_CTRL_DP (0x13U)
#define NV0073_CTRL_SVP (0x14U)
#define NV0073_CTRL_DPU (0x15U)
#define NV0073_CTRL_PSR (0x16U)
#define NV0073_CTRL_STEREO (0x17U)
/*
* NV0073_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0073_CTRL_CMD_NULL (0x730000U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl0073base_h_ */
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073common.finn
//
/*
* DSC caps -
* bDscSupported
* If GPU supports DSC or not
*
* encoderColorFormatMask
* Mask of all color formats for which DSC
* encoding is supported by GPU
*
* lineBufferSizeKB
* Size of line buffer.
*
* rateBufferSizeKB
* Size of rate buffer per slice.
*
* bitsPerPixelPrecision
* Bits per pixel precision for DSC e.g. 1/16, 1/8, 1/4, 1/2, 1bpp
*
* maxNumHztSlices
* Maximum number of horizontal slices supported by DSC encoder
*
* lineBufferBitDepth
* Bit depth used by the GPU to store the reconstructed pixels within
* the line buffer
*/
#define NV0073_CTRL_CMD_DSC_CAP_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS {
NvBool bDscSupported;
NvU32 encoderColorFormatMask;
NvU32 lineBufferSizeKB;
NvU32 rateBufferSizeKB;
NvU32 bitsPerPixelPrecision;
NvU32 maxNumHztSlices;
NvU32 lineBufferBitDepth;
} NV0073_CTRL_CMD_DSC_CAP_PARAMS;
/*
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior
* cmd
* This parameter is an input to this command.
* Here are the current defined fields:
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER
* Set to specify what operation to run.
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP
* Request to power up pad.
* NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN
* Request to power down the pad.
* linkBw
* This parameter is used to pass in the link bandwidth required to run the
* power up sequence. Refer enum DM_FRL_LINK_RATE_GBPS for valid values.
* laneCount
* This parameter is used to pass the lanecount.
* sorIndex
* This parameter is used to pass the SOR index.
* padlinkIndex
* This parameter is used to pass the padlink index for primary link.
* Please refer enum DFPPADLINK for valid index values for Link A~F.
*/
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD (0x730502U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_COMMON_INTERFACE_ID << 8) | NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS {
NvU32 subDeviceInstance;
NvU32 cmd;
NvU32 linkBw;
NvU32 laneCount;
NvU32 sorIndex;
NvU32 padlinkIndex;
} NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_PARAMS;
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER 0:0
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_UP (0x00000000U)
#define NV0073_CTRL_CMD_FRL_CONFIG_MACRO_PAD_CMD_POWER_DOWN (0x00000001U)
/* _ctrl0073common_h_ */
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
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lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
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lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
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/*
* SPDX-FileCopyrightText: Copyright (c) 2011-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073dpu.finn
//
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
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/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073event.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/*
* tilemask
* Tiles assocaited with calc tiemout head.
* frameActive
* New frame has started on this Head.
* histoReady
* Asserts when histogram data from all the "enabled" LTMs belonging to this head
* is ready.
* startFrameReady
* When histo_ready interrupt
* is received and HDMA is programmed and then RISCV asserts STARTFRAME_READY.
*/
typedef struct NV0073_LTM_HEAD_STATUS_PARAMS {
NvU8 tileMask;
NvBool frameActive;
NvBool histoReady;
NvBool startFrameReady;
} NV0073_LTM_HEAD_STATUS_PARAMS;
/* NV04_DISPLAY_COMMON event-related control commands and parameters */
/*
* NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION
*
* This command sets event notification state for the associated display
* object. This command requires that an instance of NV01_EVENT has been
* previously bound to the associated display object.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* hEvent
* This parameter specifies the handle of the NV01_EVENT instance
* to be bound to the given subDeviceInstance.
* event
* This parameter specifies the type of event to which the specified
* action is to be applied. This parameter must specify a valid
* NV0073_NOTIFIERS value (see cl0073.h for more details) and should
* not exceed one less NV0073_NOTIFIERS_MAXCOUNT.
* action
* This parameter specifies the desired event notification action.
* Valid notification actions include:
* NV0073_CTRL_SET_EVENT_NOTIFICATION_DISABLE
* This action disables event notification for the specified
* event for the associated subdevice object.
* NV0073_CTRL_SET_EVENT_NOTIFICATION_SINGLE
* This action enables single-shot event notification for the
* specified event for the associated subdevice object.
* NV0073_CTRL_SET_EVENT_NOTIFICATION_REPEAT
* This action enables repeated event notification for the specified
* event for the associated system controller object.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0073_CTRL_CMD_EVENT_SET_NOTIFICATION (0x730301U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_EVENT_INTERFACE_ID << 8) | NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
NvU32 subDeviceInstance;
NvHandle hEvent;
NvU32 event;
NvU32 action;
} NV0073_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
/* valid action values */
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_DISABLE (0x00000000U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_SINGLE (0x00000001U)
#define NV0073_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002U)
/* _ctrl0073event_h_ */
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
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/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073internal.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
#include "ctrl/ctrl0073/ctrl0073system.h"
#include "ctrl/ctrl0073/ctrl0073dfp.h"
#define NV0073_CTRL_CMD_INTERNAL_GET_HOTPLUG_UNPLUG_STATE (0x730401U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS_MESSAGE_ID (0x1U)
typedef NV0073_CTRL_SYSTEM_GET_HOTPLUG_UNPLUG_STATE_PARAMS NV0073_CTRL_INTERNAL_GET_HOTPLUG_UNPLUG_STATE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE (0x730402U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS_MESSAGE_ID (0x2U)
typedef NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS NV0073_CTRL_CMD_INTERNAL_VRR_SET_RGLINE_ACTIVE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX (0x730460U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS_MESSAGE_ID (0x3U)
typedef NV0073_CTRL_CMD_DFP_SWITCH_DISP_MUX_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_SWITCH_DISP_MUX_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS (0x730404U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS_MESSAGE_ID (0x4U)
typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_DFP_GET_DISP_MUX_STATUS_PARAMS;
/* ctrl0073internal_h */
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073psr.h
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/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073psr.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/* NV04_DISPLAY_COMMON psr-display-specific control commands and parameters */
/*
* NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO
*
* displayId
* Display ID on which this information is being requested.
* frameLockPin
* Returns the frame lock pin of the panel.
* i2cAddress
* Returns the i2c address on which the SR panel is attached.
* NOTE: applies only to LVDS panels, otherwise this field
* should be ignored.
* bSelfRefreshEnabled
* Returns whether SR is enabled in RM.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_PSR_GET_SR_PANEL_INFO (0x731602U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_PSR_INTERFACE_ID << 8) | NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS {
NvU32 displayId;
NvU32 frameLockPin;
NvU8 i2cAddress;
NvBool bSelfRefreshEnabled;
} NV0073_CTRL_PSR_GET_SR_PANEL_INFO_PARAMS;
/* _ctrl0073psr_h_ */
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/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073stereo.finn
//
#include "ctrl/ctrl0073/ctrl0073base.h"
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED
*
* This command returns the support status of the NV stereo emitter
* (also known as the stereo dongle). It reports if the stereo dongle
* is present in terms of the USB interface initialized in Resman.
* This provides a RmControl interface to the STEREO_DONGLE_SUPPORTED
* command in stereoDongleControl.
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleControl
* [IN] bI2cEmitter - I2C driven DT embedded emitter
* [IN] bForcedSupported - GPIO23 driven emitter
* [OUT] support - the control word returned by stereoDongleControl
*
* Possible status values returned are:
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_SUPPORTED (0x731702U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
NvBool bI2cEmitter;
NvBool bForcedSupported;
NvU32 support;
} NV0073_CTRL_STEREO_DONGLE_SUPPORTED_PARAMS;
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS
*
* Sets new video mode timings
* E.g. from display driver on mode set
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleControl
* [IN] timings - new timings to be set
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_SET_TIMINGS (0x731703U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID" */
typedef struct NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS {
NvU32 PixelClock;
NvU16 TotalWidth;
NvU16 VisibleImageWidth;
NvU16 HorizontalBlankStart;
NvU16 HorizontalBlankWidth;
NvU16 HorizontalSyncStart;
NvU16 HorizontalSyncWidth;
NvU16 TotalHeight;
NvU16 VisibleImageHeight;
NvU16 VerticalBlankStart;
NvU16 VerticalBlankHeight;
NvU16 VerticalSyncStart;
NvU16 VerticalSyncHeight;
NvU16 InterlacedMode;
NvU16 DoubleScanMode;
NvU16 MonitorVendorId;
NvU16 MonitorProductId;
} NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS;
#define NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
NV0073_CTRL_STEREO_VIDEO_MODE_TIMINGS timings;
} NV0073_CTRL_STEREO_DONGLE_SET_TIMINGS_PARAMS;
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE
*
* stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_YES
* Updates sbios of 3D stereo state active
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleActivate
* [IN] bSDA - enable stereo on DDC SDA
* [IN] bWorkStation - is workstation stereo?
* [IN] bDLP - is checkerboard DLP Stereo?
* [IN] IRPower - IR power value
* [IN] flywheel - FlyWheel value
* [IN] bRegIgnore - use reg?
* [IN] bI2cEmitter - Sets NV_STEREO_DONGLE_ACTVATE_DATA_I2C_EMITTER_YES and pStereo->bAegisDT
* [IN] bForcedSupported - Sets NV_STEREO_DONGLE_FORCED_SUPPORTED_YES and pStereo->GPIOControlledDongle
* [IN] bInfoFrame - Aegis DT with DP InfoFrame
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS)
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_ACTIVATE (0x731704U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
NvBool bSDA;
NvBool bWorkStation;
NvBool bDLP;
NvU8 IRPower;
NvU8 flywheel;
NvBool bRegIgnore;
NvBool bI2cEmitter;
NvBool bForcedSupported;
NvBool bInfoFrame;
} NV0073_CTRL_STEREO_DONGLE_ACTIVATE_PARAMS;
/*
* NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE
*
* stereoDongleActivate wrapper / NV_STEREO_DONGLE_ACTIVATE_DATA_ACTIVE_NO
*
* If active count<=0 then no 3D app is running which indicates
* that we have really deactivated the stereo, updates sbios of 3D stereo state NOT ACTIVE.
*
* Parameters:
* [IN] subDeviceInstance - This parameter specifies the subdevice instance
* within the NV04_DISPLAY_COMMON parent device to which the operation
* should be directed. This parameter must specify a value between
* zero and the total number of subdevices within the parent device.
* This parameter should be set to zero for default behavior.
* [IN] head - head to be passed to stereoDongleActivate
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT - if (head > OBJ_MAX_HEADS)
* NV_ERR_NOT_SUPPORTED - stereo is not initialized on the GPU
*/
#define NV0073_CTRL_CMD_STEREO_DONGLE_DEACTIVATE (0x731705U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_STEREO_INTERFACE_ID << 8) | NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS {
NvU32 subDeviceInstance;
NvU32 head;
} NV0073_CTRL_STEREO_DONGLE_DEACTIVATE_PARAMS;
/* _ctrl0073stereo_h_ */
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
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/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0073/ctrl0073svp.finn
//
lact-daemon/include/nvidia/src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
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