[GPU] Fix twin tranformer functional regression. (#16111)
* [GPU] Fix twin tranformer functional regression. gemm/FC select_preferred_format select simple format depends on out rank size. Signed-off-by: hyunback <hyunback.kim@intel.com>
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hyunback kim
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164db3def9
@ -1824,13 +1824,18 @@ void layout_optimizer::select_preferred_formats_for_onednn(program_node& node, d
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for (size_t idx = 0 ; idx < node.get_dependencies().size() ; idx++) {
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if (node.get_dependency(idx).is_constant())
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continue;
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node.set_preferred_input_fmt(idx, cldnn::format::bfyx);
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size_t out_rank = node.get_output_layout().get_rank();
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auto target_format = format::get_default_format(out_rank);
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node.set_preferred_input_fmt(idx, target_format);
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if (node.get_preferred_output_fmt() == format::any) {
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for (size_t usr = 0; usr < std::max<size_t>(1, node.get_users().size()); usr++)
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node.set_preferred_output_fmt(usr, cldnn::format::bfyx);
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for (size_t usr = 0; usr < std::max<size_t>(1, node.get_users().size()); usr++) {
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node.set_preferred_output_fmt(usr, target_format);
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}
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}
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GPU_DEBUG_LOG << "select_preferred_formats:" << node.id() << ": " << fmt_to_str(cldnn::format::bfyx) << " --> " << fmt_to_str(cldnn::format::bfyx)
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GPU_DEBUG_LOG << "select_preferred_formats:" << node.id() << ": " << fmt_to_str(target_format) << " --> " << fmt_to_str(target_format)
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<< " For index : " << idx << std::endl;
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}
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}
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@ -1350,6 +1350,138 @@ public:
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};
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#ifdef ENABLE_ONEDNN_FOR_GPU
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struct gemm_onednn_test_params {
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std::vector<tensor> in_shapes;
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tensor out_shape;
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tensor kernel;
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tensor pad;
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data_types data_type_in0;
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data_types data_type_in1;
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data_types data_type_in2;
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format input_format;
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data_types default_type;
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format default_format;
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};
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template <typename T>
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class GemmOneDNNTest : public ::testing::TestWithParam<T> {
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public:
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cldnn::engine& engine = get_test_engine();
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topology topology_ocl;
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topology topology_onednn;
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ExecutionConfig config_ocl;
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ExecutionConfig config_onednn;
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float tolerance = 0.0f;
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void SetUp() override {
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config_ocl.set_property(ov::intel_gpu::optimize_data(true));
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config_ocl.set_property(ov::intel_gpu::queue_type(QueueTypes::in_order));
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if (engine.get_device_info().supports_immad) {
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config_onednn.set_property(ov::intel_gpu::optimize_data(true));
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config_onednn.set_property(ov::intel_gpu::queue_type(QueueTypes::in_order));
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}
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}
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void execute(T& p) {
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auto input0_prim = get_generated_random_1d_mem(engine, get_input_layout(p, 0));
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auto input1_prim = get_generated_random_1d_mem(engine, get_input_layout(p, 1));
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network network_ocl(engine, topology_ocl, config_ocl);
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network network_onednn(engine, topology_onednn, config_onednn);
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network_ocl.set_input_data("input0", input0_prim);
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network_ocl.set_input_data("input1", input1_prim);
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network_onednn.set_input_data("input0", input0_prim);
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network_onednn.set_input_data("input1", input1_prim);
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compare(network_ocl, network_onednn, p);
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}
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void compare(network& network_ocl, network& network_onednn, T& p) {
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auto outputs_ocl = network_ocl.execute();
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auto outputs_onednn = network_onednn.execute();
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ASSERT_EQ(outputs_ocl.size(), outputs_onednn.size());
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ASSERT_EQ(outputs_ocl.size(), size_t(1));
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auto val_ocl = get_output_values_to_float(network_ocl, outputs_ocl.begin()->first);
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auto val_onednn = get_output_values_to_float(network_onednn, outputs_onednn.begin()->first);
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ASSERT_EQ(val_ocl.size(), val_onednn.size());
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for (size_t i = 0; i < val_ocl.size(); i++) {
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ASSERT_NEAR(val_ocl[i], val_onednn[i], tolerance)
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<< "tolerance = " << tolerance
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<< "\ni = " << i
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<< "\nocl[i] = " << val_ocl[i]
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<< "\nonednn[i] = " << val_onednn[i];
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}
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}
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layout get_input_layout(T& p, int in_no) {
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auto pad = p.pad;
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std::vector<int> pad_ = { 0, 0, pad.spatial[0], pad.spatial[1] };
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if (in_no == 0)
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return layout{ p.data_type_in0, p.input_format, p.in_shapes.at(0), padding{ pad_ } };
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else if (in_no == 1)
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return layout{ p.data_type_in1, p.input_format, p.in_shapes.at(1), padding{ pad_ } };
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else
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return layout{ p.data_type_in2, p.input_format, p.in_shapes.at(2), padding{ pad_ } };
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}
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};
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class gemm_onednn_ndims : public GemmOneDNNTest<gemm_onednn_test_params> {};
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TEST_P(gemm_onednn_ndims, basic) {
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if (!engine.get_device_info().supports_immad)
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return;
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auto p = GetParam();
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auto in_layout0 = get_input_layout(p, 0);
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auto in_layout1 = get_input_layout(p, 1);
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topology_ocl.add(input_layout("input0", in_layout0));
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topology_ocl.add(input_layout("input1", in_layout1));
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topology_ocl.add(gemm("gemm0_ocl", { input_info("input0"), input_info("input1") }, data_types::f32, false, false, 1.f, 0.f, in_layout0.get_rank(), in_layout1.get_rank()));
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topology_ocl.add(reorder("reorder0", input_info("gemm0_ocl"), p.default_format, data_types::f32));
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topology_onednn.add(input_layout("input0", get_input_layout(p, 0)));
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topology_onednn.add(input_layout("input1", get_input_layout(p, 1)));
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topology_onednn.add(gemm("gemm0_onednn", { input_info("input0"), input_info("input1") }, data_types::f32, false, false, 1.f, 0.f, in_layout0.get_rank(), in_layout1.get_rank()));
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topology_onednn.add(reorder("reorder0", input_info("gemm0_onednn"), p.default_format, data_types::f32));
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ov::intel_gpu::ImplementationDesc gemm_impl_ocl = { p.default_format, "", impl_types::ocl };
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config_ocl.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ { "gemm0_ocl", gemm_impl_ocl } }));
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ov::intel_gpu::ImplementationDesc gemm_impl_onednn = { p.default_format, "", impl_types::onednn };
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config_onednn.set_property(ov::intel_gpu::force_implementations(ov::intel_gpu::ImplForcingMap{ { "gemm0_onednn", gemm_impl_onednn } }));
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tolerance = default_tolerance(p.default_type);
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execute(p);
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}
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#define CASE_GEMM_ONEDNN_FP16_4D { { 2, 3, 2, 2 }, { 2, 3, 2, 2 } }, { 2, 3, 2, 2 }, tensor{ 1 }, tensor{ 0 }, \
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data_types::f16, data_types::f16, data_types::f16, format::bfyx, data_types::f16, format::bfyx
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#define CASE_GEMM_ONEDNN_FP16_5D { { 1, 3, 4, 4, 4 }, { 1, 3, 4, 4, 4 } }, { 1, 3, 4, 4, 4 }, tensor{ 1 }, tensor{ 0 }, \
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data_types::f16, data_types::f16, data_types::f16, format::bfzyx, data_types::f16, format::bfzyx
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#define CASE_GEMM_ONEDNN_FP16_6D { { 2, 3, 5, 4, 3, 2 }, { 2, 3, 4, 5, 3, 2 } }, { 2, 3, 5, 5, 3, 2 }, tensor{ 1 }, tensor{ 0 }, \
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data_types::f16, data_types::f16, data_types::f16, format::bfwzyx, data_types::f16, format::bfwzyx
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#define CASE_GEMM_ONEDNN_I8_4D { { 2, 3, 2, 2 }, { 2, 3, 2, 2 } }, { 2, 3, 2, 2 }, tensor{ 1 }, tensor{ 0 }, \
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data_types::i8, data_types::i8, data_types::i8, format::bfyx, data_types::i8, format::bfyx
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#define CASE_GEMM_ONEDNN_I8_5D { { 1, 3, 4, 4, 4 }, { 1, 3, 4, 4, 4 } }, { 1, 3, 4, 4, 4 }, tensor{ 1 }, tensor{ 0 }, \
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data_types::i8, data_types::i8, data_types::i8, format::bfzyx, data_types::i8, format::bfzyx
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#define CASE_GEMM_ONEDNN_I8_6D { { 2, 3, 5, 4, 3, 2 }, { 2, 3, 4, 5, 3, 2 } }, { 2, 3, 5, 5, 3, 2 }, tensor{ 1 }, tensor{ 0 }, \
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data_types::i8, data_types::i8, data_types::i8, format::bfwzyx, data_types::i8, format::bfwzyx
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INSTANTIATE_TEST_SUITE_P(gemm_gpu, gemm_onednn_ndims, ::testing::ValuesIn(std::vector<gemm_onednn_test_params>{
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gemm_onednn_test_params{ CASE_GEMM_ONEDNN_FP16_4D },
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gemm_onednn_test_params{ CASE_GEMM_ONEDNN_FP16_5D },
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gemm_onednn_test_params{ CASE_GEMM_ONEDNN_FP16_6D },
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gemm_onednn_test_params{ CASE_GEMM_ONEDNN_I8_4D },
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gemm_onednn_test_params{ CASE_GEMM_ONEDNN_I8_5D },
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gemm_onednn_test_params{ CASE_GEMM_ONEDNN_I8_6D },
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}));
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class gemm_int8_simple_tests_onednn : public ::GemmBaseTest<gemm_base_test_params, int8_t, int8_t, float, float, int32_t> {};
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TEST_P(gemm_int8_simple_tests_onednn, basic) { auto p = GetParam(); execute(p); }
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@ -609,6 +609,23 @@ inline std::vector<float> get_output_values_to_float(cldnn::network& net, const
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}
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}
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inline cldnn::memory::ptr get_generated_random_1d_mem(cldnn::engine& engine, cldnn::layout l) {
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auto prim = engine.allocate_memory(l);
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cldnn::tensor s = l.get_tensor();
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if (l.data_type == cldnn::data_types::i8 || l.data_type == cldnn::data_types::u8) {
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VF<uint8_t> rnd_vec = generate_random_1d<uint8_t>(s.count(), -200, 200);
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set_values(prim, rnd_vec);
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} else if (l.data_type == cldnn::data_types::f16) {
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VF<FLOAT16> rnd_vec = generate_random_1d<FLOAT16>(s.count(), -1, 1);
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set_values(prim, rnd_vec);
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} else {
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VF<float> rnd_vec = generate_random_1d<float>(s.count(), -1, 1);
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set_values(prim, rnd_vec);
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}
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return prim;
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}
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double default_tolerance(cldnn::data_types dt);
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// inline void print_bin_blob(cldnn::memory& mem, std::string name)
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// {
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