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Fix for compilation issue for ARM 32-bit (#4717)

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Anna Khakimova 2021-03-11 12:13:11 +03:00 committed by GitHub
parent 8070c416be
commit 61389b5e51
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 19 additions and 24 deletions
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8
inference-engine/src/preprocessing/arm_neon/ie_preprocess_gapi_kernels_neon.cpp
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@ -257,8 +257,8 @@ CV_ALWAYS_INLINE void horizontal_4LPI(std::array<std::array<uint8_t*, 4>, chanNu
v_uint8 q2 = v_shuffle(q0, hmask);
v_uint8 q3 = v_shuffle(q1, hmask);
v_uint8 q4 = v_blend<0xCC /*0b11001100*/>(q2, v_slli_si128(q3, 4));
v_uint8 q5 = v_blend<0xCC /*0b11001100*/>(v_srli_si128(q2, 4), q3);
v_uint8 q4 = v_blend<0xCC /*0b11001100*/>(q2, v_shift_left<4>(q3));
v_uint8 q5 = v_blend<0xCC /*0b11001100*/>(v_shift_right<4>(q2), q3);
v_store_low(&dst[c][0][x], q4);
v_store_high(&dst[c][1][x], q4);
@ -334,8 +334,8 @@ CV_ALWAYS_INLINE void calcRowLinear_8UC_Impl_(std::array<std::array<uint8_t*, 4>
v_uint8 q0 = v_pack_u(r0, r1);
v_uint8 q1 = v_pack_u(r2, r3);
v_uint8 q2 = v_blend<0xCC /*0b11001100*/>(q0, v_slli_si128(q1, 4));
v_uint8 q3 = v_blend<0xCC /*0b11001100*/>(v_srli_si128(q0, 4), q1);
v_uint8 q2 = v_blend<0xCC /*0b11001100*/>(q0, v_shift_left<4>(q1));
v_uint8 q3 = v_blend<0xCC /*0b11001100*/>(v_shift_right<4>(q0), q1);
v_uint8 q4 = v_shuffle(q2, vmask);
v_uint8 q5 = v_shuffle(q3, vmask);

35
inference-engine/thirdparty/ocv/opencv_hal_neon.hpp vendored
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@ -46,6 +46,7 @@
#define OPENCV_HAL_INTRIN_NEON_HPP
#include <algorithm>
#include <cassert>
namespace cv
@ -2447,34 +2448,28 @@ CV_ALWAYS_INLINE v_uint8x16 v_shuffle(const v_uint8x16& a, const v_uint8x16& mas
#endif
}
CV_ALWAYS_INLINE v_uint8x16 v_slli_si128(const v_uint8x16& a, const int imm)
template<int shift>
CV_ALWAYS_INLINE v_uint8x16 v_slli_si128(const v_uint8x16& a)
{
uint8x16_t ret = {};
if (imm <= 0) {
ret = a.val;
}
if (imm > 15) {
ret = vdupq_n_u8(0);
} else {
ret = vextq_u8(vdupq_n_u8(0), a.val, 16 - (imm));
}
assert((shift > 0) && (shift <= 15));
uint8x16_t ret = vextq_u8(vdupq_n_u8(0), a.val, shift /*16 - (imm)*/);
return v_uint8x16(ret);
}
CV_ALWAYS_INLINE v_uint8x16 v_srli_si128(const v_uint8x16& a, const int imm)
template<int shift>
CV_ALWAYS_INLINE v_uint8x16 v_shift_right(const v_uint8x16& a)
{
uint8x16_t ret = {};
if (imm <= 0) {
ret = a.val;
}
if (imm > 15) {
ret = vdupq_n_u8(0);
} else {
ret = vextq_u8(a.val, vdupq_n_u8(0), imm);
}
assert((shift > 0) && (shift <= 15));
uint8x16_t ret = vextq_u8(a.val, vdupq_n_u8(0), shift);
return v_uint8x16(ret);
}
template<int shift>
CV_ALWAYS_INLINE v_uint8x16 v_shift_left(const v_uint8x16& a)
{
return v_slli_si128<16 - shift>(a);
}
CV_CPU_OPTIMIZATION_HAL_NAMESPACE_END
//! @endcond