IntenseWebs/openvino
3
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[IE][VPU]: Fix condition in HW tiling (#3111)

Browse Source 
Co-authored-by: kora6 <kora6@github.com>
This commit is contained in:
Aleksandr Korolev 2020-11-17 11:36:23 +03:00 committed by GitHub
parent 4e510c80c0
commit 957a1f6590
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 5 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
inference-engine/src/vpu/graph_transformer/src/middleend/hw/tiling.cpp
View File

@ -430,17 +430,12 @@ bool checkHWRestrictions(
int kernelSizeX, int kernelSizeY, int kernelSizeX, int kernelSizeY,
int kernelStride, int kernelStride,
HwOpMode mode, HwOpType type) { HwOpMode mode, HwOpType type) {
// Workaround for HW ops failure if too wide input: // Workaround for HW ops failure if too wide input
// Looks like HW operations (primarily Pooling) can // widht and small height
// use only part of available CMX, up to 1014 * 128
// bits (i.e. 1014 * 16 bytes)
// Provided HwOpMode is 16x16, this means HW needs
// to read up to 16 lines of input tensor, so each
// line mustn't exceed 1014 bytes or 507 pixels if
// precision is FP16
// More details available with the ticket #-33366 // More details available with the ticket #-33366
if (inTileWidth > 507) {
return false; if (inTileWidth > 507 && inTileHeight < 64 && type != HwOpType::POOL) {
return false;
} }
const int chansPerBlock = 1 << static_cast<int>(mode); const int chansPerBlock = 1 << static_cast<int>(mode);