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[GPU] Fix implicit concat padding offset issue in OneDNN (#11062)

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Inserting padding into oneDNN primitive has issue with implicit concat behavior.
Deconv onedNN initialized output buffer to 0 including padding area. Padding area should be reserved.
Use oneDNN offset from program_node in/out lower_padding instead of oneDNN memory desc.

Signed-off-by: hyunback <hyunback.kim@intel.com>
This commit is contained in:
hyunback kim 2022-03-21 16:57:39 +09:00 committed by GitHub
parent d7005af4a5
commit ad179980d9
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 11 additions and 21 deletions
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4
src/plugins/intel_gpu/src/graph/impls/onednn/primitive_onednn_base.h
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@ -156,13 +156,13 @@ protected:
{
auto& input = instance.input_memory(0);
auto offset = onednn::get_offset(_pd.dnnl::primitive_desc_base::src_desc(0));
auto offset = onednn::get_f_offset(instance.node.input().get_output_layout(), _pd.dnnl::primitive_desc_base::src_desc(0));
args.insert({DNNL_ARG_SRC, input.get_onednn_memory(_pd.dnnl::primitive_desc_base::src_desc(0), offset)});
}
{
auto& output = instance.output_memory();
auto offset = onednn::get_offset(_pd.dnnl::primitive_desc_base::dst_desc(0));
auto offset = onednn::get_f_offset(instance.node.get_output_layout(), _pd.dnnl::primitive_desc_base::dst_desc(0));
args.insert({DNNL_ARG_DST, output.get_onednn_memory(_pd.dnnl::primitive_desc_base::dst_desc(0), offset)});
}

26
src/plugins/intel_gpu/src/graph/impls/onednn/utils.cpp
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@ -131,23 +131,16 @@ void combine_bf_with_first_spatial_dim(cldnn::layout& l) {
l.size.spatial[last_spatial_dim_idx] = 1;
}
int64_t get_offset(dnnl::memory::desc desc) {
int64_t get_f_offset(cldnn::layout l, dnnl::memory::desc desc) {
int64_t offset = 0;
int32_t padded_idx = -1;
for (int32_t i = 0; i < DNNL_MAX_NDIMS; ++i) {
if (desc.data.padded_offsets[i] > 0) {
padded_idx = i;
break;
}
}
if (padded_idx > -1) {
if (padded_idx != 1)
throw std::runtime_error(std::string("onednn only support feature padding. Unsupported padded_idx: ") + std::to_string(padded_idx));
offset = desc.data.padded_offsets[padded_idx];
for (int32_t i = padded_idx + 1; i < desc.data.ndims; ++i) {
offset *= desc.data.padded_dims[i];
auto f_padding = l.data_padding.lower_size().feature[0];
if (f_padding != 0) {
offset = f_padding;
for (size_t i = 0; i < l.size.spatial.size(); ++i) {
offset *= l.size.spatial[i];
}
}
switch (desc.data.data_type) {
case dnnl_data_type_t::dnnl_s8:
case dnnl_data_type_t::dnnl_u8:
@ -179,11 +172,8 @@ dnnl::memory::desc layout_to_memory_desc(cldnn::layout l, dnnl::memory::format_t
padded_dims = dims;
} else {
auto rank = cldnn::format::dimension(l.format);
auto padded_size = l.size + l.data_padding.lower_size() + l.data_padding.upper_size();
auto offset = l.data_padding.lower_size();
dims = convert_tensor(l.size, rank, cldnn::format::is_grouped(l.format));
padded_dims = convert_tensor(padded_size, rank);
padded_offset = convert_tensor(offset, rank);
padded_dims = dims;
}
pad_dims(padded_dims, l.format);

2
src/plugins/intel_gpu/src/graph/impls/onednn/utils.hpp
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@ -33,7 +33,7 @@ dnnl::memory::desc layout_to_memory_desc(cldnn::layout l, dnnl::memory::format_t
dnnl::algorithm convert_activation_func(cldnn::activation_func func);
cldnn::format find_format(dnnl::memory::desc desc, bool is_grouped = false);
int64_t get_offset(dnnl::memory::desc desc);
int64_t get_f_offset(cldnn::layout l, dnnl::memory::desc desc);
// If the values in the tensor are identical, make it as per-tensor value
template <typename T>