From c9d5d95e2c2a51e3e9d0efc54d0110ffbf5908d2 Mon Sep 17 00:00:00 2001 From: Ilya Lavrenov Date: Thu, 11 Mar 2021 16:02:25 +0300 Subject: [PATCH] Blocked dims hwc 2021/3 (#4729) * Fix for BlockedDims * Added test for HWC layout --- .../src/inference_engine/ie_layouts.cpp | 2 +- .../inference_engine/tensor_desc_test.cpp | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/inference-engine/src/inference_engine/ie_layouts.cpp b/inference-engine/src/inference_engine/ie_layouts.cpp index 5def2480cfd..bf49c8ad4f8 100644 --- a/inference-engine/src/inference_engine/ie_layouts.cpp +++ b/inference-engine/src/inference_engine/ie_layouts.cpp @@ -325,7 +325,7 @@ BlockingDesc::BlockingDesc(const SizeVector& dims, Layout layout): offsetPadding case Layout::HWC: checkDims(dims.size(), 3); l_order = {1, 2, 0}; - l_dims = dims; + l_dims = {dims[1], dims[2], dims[0]}; break; case Layout::CN: checkDims(dims.size(), 2); diff --git a/inference-engine/tests/functional/inference_engine/tensor_desc_test.cpp b/inference-engine/tests/functional/inference_engine/tensor_desc_test.cpp index 10dcbc696ae..0401ed85b92 100644 --- a/inference-engine/tests/functional/inference_engine/tensor_desc_test.cpp +++ b/inference-engine/tests/functional/inference_engine/tensor_desc_test.cpp @@ -44,6 +44,19 @@ TEST_F(TensorDescTests, CreateBlockedBlobNCDHW) { ASSERT_EQ(Layout::BLOCKED, blockedBlob->getTensorDesc().getLayout()); } +TEST_F(TensorDescTests, CompareHWCandCHWLayouts) { + TensorDesc descCHW(Precision::FP32, {1, 3, 4}, Layout::CHW); + TensorDesc descHWC(Precision::FP32, {1, 3, 4}, Layout::HWC); + SizeVector chw = {0, 1, 2}; + SizeVector hwc = {1, 2, 0}; + + ASSERT_NE(descCHW, descHWC); + ASSERT_NE(descCHW.getBlockingDesc(), descHWC.getBlockingDesc()); + ASSERT_NE(descCHW.getBlockingDesc().getOrder(), descHWC.getBlockingDesc().getOrder()); + ASSERT_EQ(descCHW.getBlockingDesc().getOrder(), chw); + ASSERT_EQ(descHWC.getBlockingDesc().getOrder(), hwc); +} + TEST_F(TensorDescTests, CompareNHWCandNCHWLayouts) { TensorDesc descNCHW(Precision::FP32, {1, 3, 4, 2}, Layout::NCHW); TensorDesc descNHWC(Precision::FP32, {1, 3, 4, 2}, Layout::NHWC);