[IE][VPU][GT] Add pass to reshape convolution by parameter from IR (#3038)

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George Zlobin 2020-12-21 17:39:19 +03:00 committed by GitHub
parent a497153dcd
commit e490dfc161
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7 changed files with 135 additions and 0 deletions

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@ -547,6 +547,10 @@ std::shared_ptr<ngraph::Node> V10Parser::createNode(const std::vector<ngraph::Ou
if (pr_data) {
rtInfo["PrimitivesPriority"] = std::make_shared<::ngraph::VariantWrapper<std::string> >(pr_data.value());
}
const auto aw_data = dn.attribute("alt_width");
if (aw_data) {
rtInfo["alt_width"] = std::make_shared<::ngraph::VariantWrapper<std::string> >(aw_data.value());
}
}
ngraphNode->set_friendly_name(params.name);

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@ -112,6 +112,7 @@ struct CompilationConfig final {
bool forcePureTensorIterator = false;
bool enableMemoryTypesAnnotation = false;
bool enableWeightsAnalysis = true;
bool enableCustomReshapeParam = false;
//
// Deprecated options

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@ -249,6 +249,8 @@ public:
Pass::Ptr annotateMemoryTypes();
Pass::Ptr reshapeBeforeConvTiling();
protected:
StageBuilder::Ptr _stageBuilder;
BackEnd::Ptr _backEnd;

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@ -44,6 +44,13 @@ DECLARE_VPU_CONFIG(MYRIAD_ENABLE_EARLY_ELTWISE_RELU_FUSION);
*/
DECLARE_VPU_CONFIG(MYRIAD_ENABLE_WEIGHTS_ANALYSIS);
/**
* @brief Used to enable reshapeBeforeConvTiling pass in cases where
* user have reshape parameter "alt_width" in IR.
* Default is "NO".
*/
DECLARE_VPU_CONFIG(MYRIAD_ENABLE_CUSTOM_RESHAPE_PARAM);
//
// Debug options
//

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@ -166,6 +166,18 @@ PassSet::Ptr PassManager::buildMiddleEnd() {
ADD_DUMP_PASS("reshapeDilationConv");
}
//
// "reshapeBeforeConvTiling" pass changes geometry of convolution stages in order
// to get more efficient HW tiling (pass "hwConvTiling") using reshape stages.
//
// Pass should be located before "adjustDataBatch" because "adjustDataBatch" specifies "origConvOutput" attribute
// for convolution in order to provide that information to "hwConvTiling" pass.
// Otherwise, "hwConvTiling" will see incorrect values in "origConvOutput" attribute.
if (env.config.enableCustomReshapeParam) {
ADD_PASS(reshapeBeforeConvTiling);
ADD_DUMP_PASS("reshapeBeforeConvTiling");
}
ADD_PASS(upliftActivationStages);
ADD_DUMP_PASS("upliftActivationStages");

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@ -0,0 +1,107 @@
// Copyright (C) 2020 Intel Corporation
// SPDX-License-Identifier: Apache-2.0
//
// This pass changes geometry of convolution stages in order
// to get more efficient HW tiling (pass "hwConvTiling") using reshape stages.
#include <vpu/middleend/pass_manager.hpp>
namespace vpu {
namespace {
class PassImpl final : public Pass {
public:
explicit PassImpl(const StageBuilder::Ptr& stageBuilder) : _stageBuilder(stageBuilder) {}
void run(const Model& model) override;
private:
StageBuilder::Ptr _stageBuilder;
};
void PassImpl::run(const Model& model) {
VPU_PROFILE(reshapeBeforeConvTiling);
for (const auto& stage : model->getStages()) {
if (stage->type() != StageType::StubConv) {
continue;
}
const auto tryHW = stage->attrs().getOrDefault<bool>("tryHW", false);
if (!tryHW) {
continue;
}
const auto input = stage->input(0);
const auto output = stage->output(0);
const auto& inputDesc = input->desc();
const auto& outputDesc = output->desc();
if ((inputDesc.dimsOrder() != DimsOrder::NCHW) ||
(outputDesc.dimsOrder() != DimsOrder::NCHW)) {
continue;
}
if (stage->attrs().get<int>("kernelSizeX") != 1 ||
stage->attrs().get<int>("kernelSizeY") != 1)
continue;
int dimH = inputDesc.dim(Dim::H);
int dimW = inputDesc.dim(Dim::W);
int resultH = 0;
int resultW = 0;
if (stage->origLayer()->params.count("alt_width")) {
const auto alt_width = stage->origLayer()->params.at("alt_width");
if (!alt_width.empty() &&
std::find_if(alt_width.begin(), alt_width.end(),
[](unsigned char c) { return !std::isdigit(c); }) == alt_width.end()) {
resultW = std::stoul(alt_width);
}
}
if (resultW == 0) {
continue;
}
resultH = dimH * dimW / resultW;
IE_ASSERT(dimH * dimW == resultH * resultW);
auto inputNewDesc = inputDesc;
inputNewDesc.setDim(Dim::W, resultW);
inputNewDesc.setDim(Dim::H, resultH);
auto outputNewDesc = outputDesc;
outputNewDesc.setDim(Dim::W, resultW);
outputNewDesc.setDim(Dim::H, resultH);
auto newInput = model->duplicateData(input, "@input-data-after-reshape",
inputNewDesc);
auto newOutput = model->duplicateData(output, "@output-data-before-reshape",
outputNewDesc);
model->replaceStageInput(stage->inputEdge(0), newInput);
model->replaceStageOutput(stage->outputEdge(0), newOutput);
_stageBuilder->addReshapeStage(model,
stage->name() + "@copy-reinterpret-input-data",
nullptr, input, newInput);
_stageBuilder->addReshapeStage(model,
stage->name() + "@copy-reinterpret-output-data",
nullptr, newOutput, output);
}
}
} // namespace
Pass::Ptr PassManager::reshapeBeforeConvTiling() {
return std::make_shared<PassImpl>(_stageBuilder);
}
} // namespace vpu

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@ -69,6 +69,7 @@ IE_SUPPRESS_DEPRECATED_START
ie::MYRIAD_DISABLE_CONVERT_STAGES,
ie::MYRIAD_ENABLE_WEIGHTS_ANALYSIS,
ie::MYRIAD_ENABLE_EARLY_ELTWISE_RELU_FUSION,
ie::MYRIAD_ENABLE_CUSTOM_RESHAPE_PARAM,
//
// Debug options
@ -186,6 +187,7 @@ void ParsedConfig::parse(const std::map<std::string, std::string>& config) {
setOption(_compileConfig.disableConvertStages, switches, config, ie::MYRIAD_DISABLE_CONVERT_STAGES);
setOption(_compileConfig.enableWeightsAnalysis, switches, config, ie::MYRIAD_ENABLE_WEIGHTS_ANALYSIS);
setOption(_compileConfig.enableEarlyEltwiseReLUFusion, switches, config, ie::MYRIAD_ENABLE_EARLY_ELTWISE_RELU_FUSION);
setOption(_compileConfig.enableCustomReshapeParam, switches, config, ie::MYRIAD_ENABLE_CUSTOM_RESHAPE_PARAM);
setOption(_compileConfig.irWithVpuScalesDir, config, ie::MYRIAD_IR_WITH_SCALES_DIRECTORY);
setOption(_compileConfig.noneLayers, config, ie::MYRIAD_NONE_LAYERS, parseStringSet);