* Try fix parsing error.
* Small exception refinements during importing model.
* More exception refinements.
* Skip segfaulting tests.
* More clear error types and messages. Func rename.
* Fix typo.
* Check on CI whether test_onnx will work.
* Add only those file which pass tests or have failing ones skipped.
* Extend nGraph for operation CTCLoss
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
* Fixes as per comments
Co-authored-by: Nikolay Shchegolev <nikolay.shchegolev@intel.com>
* Add mish op to ngraph
* Update mish op
* Set v4 namespase for tests
* Add mish to cmake
* Add comments for mish op.
* Refactoring code style
* Update version to v1 for Mish op
* Add value propogation test for Mish op
* Refactoring mish op according to review
* Fix mish version
* Update cmake file
* Fix mish value propogation unit test
* Add unit test for mish op
Co-authored-by: Your Name <you@example.com>
* [Stress] Define Database constant arguments in memcheck_upload.py only
* [Stress] Simplify computations using HashableDict in `compare_memcheck_2_runs`
* [Stress] Add comparison using pandas
* Some pass creates datas duplicate with a different order from time to time (because of unordered_set usage). It leads to a different order in model->datas() list and affects the shape allocation process which relies on this order.
* Make shape allocation be relied on topological order of datas which is stable and doesn't depend on order datas creation during different passes.
Don't increment mapped_idx via prefix increment within the argument of the
potentially unsafe CPU_ISSET_S macro. If the macro is expanded so that the
increment expression is evaluated multiple times, it will return unexpected
results.
While the glibc implementation of CPU_ISSET_S macro seems to be safe, the musl
libc (v1.1.23) version is unsafe and will evaluate the first argument of
CPU_ISSET_S three times.
Co-authored-by: Christian Priebe <cp3213@ic.ac.uk>
In some networks, mvTensor would request a large CMX-DMA transfer (<512K). That starves DMA for other timing critical tasks such as SIPP. Limit CMX-DMA request size as an option in myriad_compile:
* Add compile option TILING_CMX_LIMIT_KB
* Declare compile option TILING_CMX_LIMIT_KB in IE tools (compile_tool and vpu_compile)
* Add tests for compile option TILING_CMX_LIMIT_KB. Small fix for naming behavior tests.
* Specify operation CTCLoss-4
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
* Correct documentation for CTCLoss after #1 review
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
* Correct documentation for CTCLoss after #2 review
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
* Correct documentation for CTCLoss after #3 review
* Correct documentation for CTCLoss after #4 review
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
* Correct layout for logits and add more description for unique attribute
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
* Correct types for length and indices tensors
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
* Correct formulas and punctuation
Signed-off-by: Roman Kazantsev <roman.kazantsev@intel.com>
