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11 Commits
Author SHA1 Message Date
Anastasia Popova bfc6e617a7 Updated RandomUniform spec to align with the implementation. (#7491) 2021-09-15 10:26:39 +03:00
Gabriele Galiero Casay 8d4e850356 Fix op category section in operations spec (#7130) 2021-08-23 13:12:46 +03:00
Anastasia Popova f26ecdd53f Corrected formulas rendering. (#6986) 2021-08-12 13:08:43 +03:00
Anastasia PopovaandTatiana Savina c776ea90d8 Added specification for RandomUniform operation. (#6196) 
* Added RandomUniform specification.

* Extended description of obtaining float numbers.

* Added description of obtainin float16 and double values.

* Added description of xor symbol.

* Small correction.

* Small corrections.

* Added initial type attribute.

* Corrected IR example, removed unnecessary default values.

* Small correction.

* Added information about type cast between initial and output types.

* Removed initial type attribute.

* Corrected output_type description.

* Corrected minval, maxval description. Corrected IR example.

* Apply suggestions from code review

Co-authored-by: Tatiana Savina <tatiana.savina@intel.com>

* Removed unnecessary paper link.

Co-authored-by: Tatiana Savina <tatiana.savina@intel.com>
 2021-07-23 14:22:53 +03:00
Patryk Elszkowski 39afcb2e99 use floating-point in docs (#6659) 
* use `floating-point` in docs

* Get back capital letter.
 2021-07-16 07:48:45 +03:00
Patryk Elszkowski b9d02939b3 remove **Default value**: None when **Required**: *yes* (#6638) 2021-07-14 15:00:29 +03:00
Patryk Elszkowski de53c40578 bulk change type T to type *T* in spec (#6486) 
* bulk change `type T` to `type *T*` in spec

* update all `T` which referee to type to use *T* pattern

* get back with `T` where T is dimension

* fix *T*1 -> *T1*

* Make italic types where was no formating
 2021-07-02 13:51:00 +03:00
Evgeny Lazarev 93074590de Updated operations specification documents (2021.2) (#2270) 
* Updated documentation structure and remove incorrect added files for Acosh-1, Asinh-1 and Atanh-1

* Fixed broken links
 2020-09-18 08:16:14 +03:00
Maxim Vafin c10c80bdca Specify Range-4 operation (#1180) 2020-07-24 14:37:32 +03:00
Nikolay Tyukaevanddomi2000 ef45b5da8d Doc Migration (master) (#1377) 
* Doc Migration from Gitlab (#1289)

* doc migration

* fix

* Update FakeQuantize_1.md

* Update performance_benchmarks.md

* Updates graphs for FPGA

* Update performance_benchmarks.md

* Change DL Workbench structure (#1)

* Changed DL Workbench structure

* Fixed tags

* fixes

* Update ie_docs.xml

* Update performance_benchmarks_faq.md

* Fixes in DL Workbench layout

* Fixes for CVS-31290

* [DL Workbench] Minor correction

* Fix for CVS-30955

* Added nGraph deprecation notice as requested by Zoe

* fix broken links in api doxy layouts

* CVS-31131 fixes

* Additional fixes

* Fixed POT TOC

* Update PAC_Configure.md

PAC DCP 1.2.1 install guide.

* Update inference_engine_intro.md

* fix broken link

* Update opset.md

* fix

* added opset4 to layout

* added new opsets to layout, set labels for them

* Update VisionAcceleratorFPGA_Configure.md

Updated from 2020.3 to 2020.4

Co-authored-by: domi2000 <domi2000@users.noreply.github.com>
 2020-07-20 17:36:08 +03:00
Andrey Zaytsev d67371617a Added opset docs (#992) 2020-06-19 14:39:57 +03:00