mirror of
https://github.com/Lurkki14/tuxclocker.git
synced 2025-02-25 18:55:24 -06:00
More xnvctrl code and start adding nvml code
This commit is contained in:
jussi
parent
57017386a3
commit
2ac0d2d1e9
138
nvidia.cpp
138
nvidia.cpp
@ -9,6 +9,7 @@ nvidia::nvidia(QObject *parent) : QObject(parent)
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}
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bool nvidia::setupXNVCtrl()
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{
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setupNVML();
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// Open the x-server connection and check if the extension exists
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dpy = XOpenDisplay(nullptr);
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Bool ret;
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@ -78,22 +79,86 @@ void nvidia::queryGPUFeatures()
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Bool ret;
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NVCTRLAttributeValidValuesRec values;
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for (int i=0; i<gpuCount; i++) {
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// Query if voltage offset is writable/readable
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ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_GPU_OVER_VOLTAGE_OFFSET,
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&values);
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qDebug() << values.u.range.max << values.permissions << "value";
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if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
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GPUList[i].overVoltAvailable = true;
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GPUList[i].voltageReadable = true;
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// If the feature is writable save the offset range
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GPUList[i].minVoltageOffset = values.u.range.min;
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GPUList[i].minVoltageOffset = values.u.range.max;
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//qDebug() << values.u.range.min << values.u.range.max << "offset range";
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} else {
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// Check if it's readable
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if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
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GPUList[i].voltageReadable = true;
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}
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}
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GPUList[i].maxVoltageOffset = values.u.range.max;
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// Query if core clock offset is writable
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ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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3,
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NV_CTRL_GPU_NVCLOCK_OFFSET,
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&values);
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if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
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GPUList[i].overClockAvailable = true;
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GPUList[i].minCoreClkOffset = values.u.range.min;
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GPUList[i].maxCoreClkOffset = values.u.range.max;
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//qDebug() << values.u.range.min << values.u.range.max << "offset range";
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} else {
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if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
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GPUList[i].coreClkReadable = true;
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}
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}
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// Query if memory clock offset is writable
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ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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3,
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NV_CTRL_GPU_MEM_TRANSFER_RATE_OFFSET,
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&values);
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if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
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GPUList[i].memOverClockAvailable = true;
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GPUList[i].minMemClkOffset = values.u.range.min;
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GPUList[i].maxMemClkOffset = values.u.range.max;
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qDebug() << values.u.range.min << values.u.range.max << "offset range";
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} else {
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if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
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GPUList[i].memClkReadable = true;
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}
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}
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// Query fan control permissions
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int retval;
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ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_GPU_COOLER_MANUAL_CONTROL,
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&retval);
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if ((retval & NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE) == NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE) {
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qDebug() << "fanctl on";
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GPUList[i].manualFanCtrl = true;
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}
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}
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queryGPUVoltage(0);
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queryGPUTemp(0);
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queryGPUFrequency(0);
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queryGPUFrequencies(0);
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queryGPUFanSpeed(0);
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//assignFanSpeed(0, 60);
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//assignGPUFanSpeed(0, 60);
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//assignGPUFreqOffset(0, 10);
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//assignGPUMemClockOffset(0, 10);
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//assignGPUVoltageOffset(0, 5000);
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assignGPUFanCtlMode(0, NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE);
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}
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void nvidia::queryGPUVoltage(int GPUIndex)
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{
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@ -120,7 +185,7 @@ void nvidia::queryGPUTemp(int GPUIndex)
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&GPUList[GPUIndex].temp);
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qDebug() << GPUList[GPUIndex].temp;
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}
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void nvidia::queryGPUFrequency(int GPUIndex)
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void nvidia::queryGPUFrequencies(int GPUIndex)
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{
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Bool ret;
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int packedInt = 0;
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@ -151,7 +216,7 @@ void nvidia::queryGPUFanSpeed(int GPUIndex)
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qDebug() << GPUList[GPUIndex].fanSpeed;
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}
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bool nvidia::assignFanSpeed(int GPUIndex, int targetValue)
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bool nvidia::assignGPUFanSpeed(int GPUIndex, int targetValue)
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{
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Bool ret;
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ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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@ -162,6 +227,49 @@ bool nvidia::assignFanSpeed(int GPUIndex, int targetValue)
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targetValue);
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return ret;
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}
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bool nvidia::assignGPUFanCtlMode(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_GPU_COOLER_MANUAL_CONTROL,
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targetValue);
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return ret;
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}
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bool nvidia::assignGPUFreqOffset(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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3, // This argument is the performance mode
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NV_CTRL_GPU_NVCLOCK_OFFSET,
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targetValue);
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qDebug() << ret << "freqassign";
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return ret;
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}
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bool nvidia::assignGPUMemClockOffset(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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3,
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NV_CTRL_GPU_MEM_TRANSFER_RATE_OFFSET,
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targetValue);
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qDebug() << ret << "memassign";
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return ret;
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}
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bool nvidia::assignGPUVoltageOffset(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_GPU_OVER_VOLTAGE_OFFSET,
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targetValue);
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qDebug() << ret;
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return ret;
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}
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/*bool nvidia::setup()
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{
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dpy = XOpenDisplay(nullptr);
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@ -175,3 +283,21 @@ bool nvidia::assignFanSpeed(int GPUIndex, int targetValue)
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qDebug() << temp;
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return true;
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}*/
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bool nvidia::setupNVML()
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{
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nvmlDevice_t dev;
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nvmlReturn_t ret = nvmlInit();
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int i;
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char name[64];
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nvmlDeviceGetHandleByIndex(i, &dev);
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nvmlDeviceGetName(dev, name, sizeof(name)/sizeof(name[0]));
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qDebug() << name << "from nvml";
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if (NVML_SUCCESS != ret) {
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return false;
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}
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return true;
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}
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void nvidia::queryGPUUtils(int GPUIndex)
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{
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}
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29
nvidia.h
29
nvidia.h
@ -4,6 +4,7 @@
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#include <QObject>
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#include <QDebug>
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#include <QtX11Extras/QX11Info>
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#include "/opt/cuda/include/nvml.h"
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class nvidia : public QObject
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{
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@ -17,15 +18,29 @@ public:
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int index;
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char *name;
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char *uuid;
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bool overVoltAvailable;
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bool overClockAvailable;
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char *utils;
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bool overVoltAvailable = false;
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bool overClockAvailable = false;
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bool memOverClockAvailable = false;
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bool voltageReadable = false;
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bool coreClkReadable = false;
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bool memClkReadable = false;
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bool manualFanCtrl = false;
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int maxVoltageOffset;
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int minVoltageOffset;
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int minCoreClkOffset;
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int maxCoreClkOffset;
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int minMemClkOffset;
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int maxMemClkOffset;
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int coreFreq;
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int memFreq;
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int temp;
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int voltage;
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int fanSpeed;
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int totalVRAM;
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int usedVRAM;
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};
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QVector <GPU> GPUList;
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int gpuCount = 0;
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@ -35,16 +50,22 @@ signals:
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public slots:
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bool setupXNVCtrl();
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bool setupNVML();
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void queryGPUCount();
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void queryGPUNames();
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void queryGPUUIDs();
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void queryGPUFeatures();
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void queryGPUVoltage(int GPUIndex);
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void queryGPUTemp(int GPUIndex);
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void queryGPUFrequency(int GPUIndex);
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void queryGPUFrequencies(int GPUIndex);
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void queryGPUFanSpeed(int GPUIndex);
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void queryGPUUtils(int GPUIndex);
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bool assignFanSpeed(int GPUIndex, int targetValue);
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bool assignGPUFanSpeed(int GPUIndex, int targetValue);
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bool assignGPUFanCtlMode(int GPUIndex, int targetValue);
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bool assignGPUFreqOffset(int GPUIndex, int targetValue);
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bool assignGPUMemClockOffset(int GPUIndex, int targetValue);
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bool assignGPUVoltageOffset(int GPUIndex, int targetValue);
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private slots:
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};
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@ -50,9 +50,9 @@ FORMS += \
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editprofile.ui \
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newprofile.ui
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INCLUDEPATH += "/usr/lib"
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INCLUDEPATH += "/usr/lib" "/lib/"
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LIBS += -lXext -lXNVCtrl -lX11
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LIBS += -lXext -lXNVCtrl -lX11 -lnvidia-ml
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# Default rules for deployment.
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qnx: target.path = /tmp/$${TARGET}/bin
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else: unix:!android: target.path = /opt/$${TARGET}/bin
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