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More xnvctrl code and start adding nvml code

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This commit is contained in:
jussi 2019-01-24 18:26:47 +02:00
parent 57017386a3
commit 2ac0d2d1e9
3 changed files with 159 additions and 12 deletions
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138
nvidia.cpp
View File

@ -9,6 +9,7 @@ nvidia::nvidia(QObject *parent) : QObject(parent)
} }
bool nvidia::setupXNVCtrl() bool nvidia::setupXNVCtrl()
{ {
setupNVML();
// Open the x-server connection and check if the extension exists // Open the x-server connection and check if the extension exists
dpy = XOpenDisplay(nullptr); dpy = XOpenDisplay(nullptr);
Bool ret; Bool ret;
@ -78,22 +79,86 @@ void nvidia::queryGPUFeatures()
Bool ret; Bool ret;
NVCTRLAttributeValidValuesRec values; NVCTRLAttributeValidValuesRec values;
for (int i=0; i<gpuCount; i++) { for (int i=0; i<gpuCount; i++) {
// Query if voltage offset is writable/readable
ret = XNVCTRLQueryValidTargetAttributeValues(dpy, ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
NV_CTRL_TARGET_TYPE_GPU, NV_CTRL_TARGET_TYPE_GPU,
i, i,
0, 0,
NV_CTRL_GPU_OVER_VOLTAGE_OFFSET, NV_CTRL_GPU_OVER_VOLTAGE_OFFSET,
&values); &values);
qDebug() << values.u.range.max << values.permissions << "value"; if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
GPUList[i].overVoltAvailable = true;
GPUList[i].voltageReadable = true;
// If the feature is writable save the offset range
GPUList[i].minVoltageOffset = values.u.range.min;
GPUList[i].minVoltageOffset = values.u.range.max;
//qDebug() << values.u.range.min << values.u.range.max << "offset range";
} else {
// Check if it's readable
if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
GPUList[i].voltageReadable = true;
}
}
GPUList[i].maxVoltageOffset = values.u.range.max; // Query if core clock offset is writable
ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
NV_CTRL_TARGET_TYPE_GPU,
i,
3,
NV_CTRL_GPU_NVCLOCK_OFFSET,
&values);
if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
GPUList[i].overClockAvailable = true;
GPUList[i].minCoreClkOffset = values.u.range.min;
GPUList[i].maxCoreClkOffset = values.u.range.max;
//qDebug() << values.u.range.min << values.u.range.max << "offset range";
} else {
if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
GPUList[i].coreClkReadable = true;
}
}
// Query if memory clock offset is writable
ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
NV_CTRL_TARGET_TYPE_GPU,
i,
3,
NV_CTRL_GPU_MEM_TRANSFER_RATE_OFFSET,
&values);
if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
GPUList[i].memOverClockAvailable = true;
GPUList[i].minMemClkOffset = values.u.range.min;
GPUList[i].maxMemClkOffset = values.u.range.max;
qDebug() << values.u.range.min << values.u.range.max << "offset range";
} else {
if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
GPUList[i].memClkReadable = true;
}
}
// Query fan control permissions
int retval;
ret = XNVCTRLQueryTargetAttribute(dpy,
NV_CTRL_TARGET_TYPE_GPU,
i,
0,
NV_CTRL_GPU_COOLER_MANUAL_CONTROL,
&retval);
if ((retval & NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE) == NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE) {
qDebug() << "fanctl on";
GPUList[i].manualFanCtrl = true;
}
} }
queryGPUVoltage(0); queryGPUVoltage(0);
queryGPUTemp(0); queryGPUTemp(0);
queryGPUFrequency(0); queryGPUFrequencies(0);
queryGPUFanSpeed(0); queryGPUFanSpeed(0);
//assignFanSpeed(0, 60); //assignGPUFanSpeed(0, 60);
//assignGPUFreqOffset(0, 10);
//assignGPUMemClockOffset(0, 10);
//assignGPUVoltageOffset(0, 5000);
assignGPUFanCtlMode(0, NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE);
} }
void nvidia::queryGPUVoltage(int GPUIndex) void nvidia::queryGPUVoltage(int GPUIndex)
{ {
@ -120,7 +185,7 @@ void nvidia::queryGPUTemp(int GPUIndex)
&GPUList[GPUIndex].temp); &GPUList[GPUIndex].temp);
qDebug() << GPUList[GPUIndex].temp; qDebug() << GPUList[GPUIndex].temp;
} }
void nvidia::queryGPUFrequency(int GPUIndex) void nvidia::queryGPUFrequencies(int GPUIndex)
{ {
Bool ret; Bool ret;
int packedInt = 0; int packedInt = 0;
@ -151,7 +216,7 @@ void nvidia::queryGPUFanSpeed(int GPUIndex)
qDebug() << GPUList[GPUIndex].fanSpeed; qDebug() << GPUList[GPUIndex].fanSpeed;
} }
bool nvidia::assignFanSpeed(int GPUIndex, int targetValue) bool nvidia::assignGPUFanSpeed(int GPUIndex, int targetValue)
{ {
Bool ret; Bool ret;
ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy, ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
@ -162,6 +227,49 @@ bool nvidia::assignFanSpeed(int GPUIndex, int targetValue)
targetValue); targetValue);
return ret; return ret;
} }
bool nvidia::assignGPUFanCtlMode(int GPUIndex, int targetValue)
{
Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
NV_CTRL_TARGET_TYPE_GPU,
GPUIndex,
0,
NV_CTRL_GPU_COOLER_MANUAL_CONTROL,
targetValue);
return ret;
}
bool nvidia::assignGPUFreqOffset(int GPUIndex, int targetValue)
{
Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
NV_CTRL_TARGET_TYPE_GPU,
GPUIndex,
3, // This argument is the performance mode
NV_CTRL_GPU_NVCLOCK_OFFSET,
targetValue);
qDebug() << ret << "freqassign";
return ret;
}
bool nvidia::assignGPUMemClockOffset(int GPUIndex, int targetValue)
{
Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
NV_CTRL_TARGET_TYPE_GPU,
GPUIndex,
3,
NV_CTRL_GPU_MEM_TRANSFER_RATE_OFFSET,
targetValue);
qDebug() << ret << "memassign";
return ret;
}
bool nvidia::assignGPUVoltageOffset(int GPUIndex, int targetValue)
{
Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
NV_CTRL_TARGET_TYPE_GPU,
GPUIndex,
0,
NV_CTRL_GPU_OVER_VOLTAGE_OFFSET,
targetValue);
qDebug() << ret;
return ret;
}
/*bool nvidia::setup() /*bool nvidia::setup()
{ {
dpy = XOpenDisplay(nullptr); dpy = XOpenDisplay(nullptr);
@ -175,3 +283,21 @@ bool nvidia::assignFanSpeed(int GPUIndex, int targetValue)
qDebug() << temp; qDebug() << temp;
return true; return true;
}*/ }*/
bool nvidia::setupNVML()
{
nvmlDevice_t dev;
nvmlReturn_t ret = nvmlInit();
int i;
char name[64];
nvmlDeviceGetHandleByIndex(i, &dev);
nvmlDeviceGetName(dev, name, sizeof(name)/sizeof(name[0]));
qDebug() << name << "from nvml";
if (NVML_SUCCESS != ret) {
return false;
}
return true;
}
void nvidia::queryGPUUtils(int GPUIndex)
{
}

29
nvidia.h
View File

@ -4,6 +4,7 @@
#include <QObject> #include <QObject>
#include <QDebug> #include <QDebug>
#include <QtX11Extras/QX11Info> #include <QtX11Extras/QX11Info>
#include "/opt/cuda/include/nvml.h"
class nvidia : public QObject class nvidia : public QObject
{ {
@ -17,15 +18,29 @@ public:
int index; int index;
char *name; char *name;
char *uuid; char *uuid;
bool overVoltAvailable; char *utils;
bool overClockAvailable; bool overVoltAvailable = false;
bool overClockAvailable = false;
bool memOverClockAvailable = false;
bool voltageReadable = false;
bool coreClkReadable = false;
bool memClkReadable = false;
bool manualFanCtrl = false;
int maxVoltageOffset; int maxVoltageOffset;
int minVoltageOffset;
int minCoreClkOffset;
int maxCoreClkOffset;
int minMemClkOffset;
int maxMemClkOffset;
int coreFreq; int coreFreq;
int memFreq; int memFreq;
int temp; int temp;
int voltage; int voltage;
int fanSpeed; int fanSpeed;
int totalVRAM;
int usedVRAM;
}; };
QVector <GPU> GPUList; QVector <GPU> GPUList;
int gpuCount = 0; int gpuCount = 0;
@ -35,16 +50,22 @@ signals:
public slots: public slots:
bool setupXNVCtrl(); bool setupXNVCtrl();
bool setupNVML();
void queryGPUCount(); void queryGPUCount();
void queryGPUNames(); void queryGPUNames();
void queryGPUUIDs(); void queryGPUUIDs();
void queryGPUFeatures(); void queryGPUFeatures();
void queryGPUVoltage(int GPUIndex); void queryGPUVoltage(int GPUIndex);
void queryGPUTemp(int GPUIndex); void queryGPUTemp(int GPUIndex);
void queryGPUFrequency(int GPUIndex); void queryGPUFrequencies(int GPUIndex);
void queryGPUFanSpeed(int GPUIndex); void queryGPUFanSpeed(int GPUIndex);
void queryGPUUtils(int GPUIndex);
bool assignFanSpeed(int GPUIndex, int targetValue); bool assignGPUFanSpeed(int GPUIndex, int targetValue);
bool assignGPUFanCtlMode(int GPUIndex, int targetValue);
bool assignGPUFreqOffset(int GPUIndex, int targetValue);
bool assignGPUMemClockOffset(int GPUIndex, int targetValue);
bool assignGPUVoltageOffset(int GPUIndex, int targetValue);
private slots: private slots:
}; };

4
rojekti.pro
View File

@ -50,9 +50,9 @@ FORMS += \
editprofile.ui \ editprofile.ui \
newprofile.ui newprofile.ui
INCLUDEPATH += "/usr/lib" INCLUDEPATH += "/usr/lib" "/lib/"
LIBS += -lXext -lXNVCtrl -lX11 LIBS += -lXext -lXNVCtrl -lX11 -lnvidia-ml
# Default rules for deployment. # Default rules for deployment.
qnx: target.path = /tmp/$${TARGET}/bin qnx: target.path = /tmp/$${TARGET}/bin
else: unix:!android: target.path = /opt/$${TARGET}/bin else: unix:!android: target.path = /opt/$${TARGET}/bin