mirror of
https://github.com/Lurkki14/tuxclocker.git
synced 2025-02-25 18:55:24 -06:00
491 lines
19 KiB
C++
491 lines
19 KiB
C++
/*This file is part of TuxClocker.
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Copyright (c) 2019 Jussi Kuokkanen
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TuxClocker is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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TuxClocker is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with TuxClocker. If not, see <https://www.gnu.org/licenses/>.*/
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#include "nvidia.h"
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#include <X11/Xlib.h>
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#include "NVCtrl/NVCtrlLib.h"
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nvidia::nvidia(QObject *parent) : QObject(parent)
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{
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}
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bool nvidia::setupXNVCtrl()
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{
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// Open the x-server connection and check if the extension exists
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dpy = XOpenDisplay(nullptr);
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Bool ret;
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int *event_basep = nullptr;
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int *error_basep = nullptr;
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ret = XNVCTRLQueryExtension(dpy,
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event_basep,
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error_basep);
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qDebug() << ret;
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queryGPUCount();
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queryGPUNames();
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queryGPUUIDs();
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queryGPUFeatures();
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return ret;
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}
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void nvidia::queryGPUCount()
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{
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Bool ret;
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ret = XNVCTRLQueryTargetCount(dpy, NV_CTRL_TARGET_TYPE_GPU, &gpuCount);
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if (!ret) {
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qDebug() << "Failed to query amount of GPUs";
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}
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// Create an appropriate number of GPU objects
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for (int i=0; i<gpuCount; i++) {
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GPU gpu;
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GPUList.append(gpu);
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}
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qDebug() << GPUList.size() << "gpus";
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//setupNVML(0);
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}
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void nvidia::queryGPUNames()
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{
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Bool ret;
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for (int i=0; i<gpuCount; i++) {
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ret = XNVCTRLQueryTargetStringAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_STRING_PRODUCT_NAME,
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&GPUList[i].name);
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if (!ret) {
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qDebug() << "Failed to query GPU Name";
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}
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qDebug() << GPUList[i].name;
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}
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}
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void nvidia::queryGPUUIDs()
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{
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Bool ret;
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for (int i=0; i<gpuCount; i++) {
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ret = XNVCTRLQueryTargetStringAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_STRING_GPU_UUID,
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&GPUList[i].uuid);
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if (!ret) {
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qDebug() << "Failed to query GPU UUID";
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}
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qDebug() << GPUList[i].uuid;
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}
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}
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void nvidia::queryGPUFeatures()
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{
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// Query static features related to the GPU such as maximum offsets here
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Bool ret;
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NVCTRLAttributeValidValuesRec values;
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for (int i=0; i<gpuCount; i++) {
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// Query all performance modes
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queryGPUMaxPerfMode(i);
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// Query if voltage offset is writable/readable
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ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_GPU_OVER_VOLTAGE_OFFSET,
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&values);
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if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
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GPUList[i].overVoltAvailable = true;
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GPUList[i].voltageReadable = true;
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// If the feature is writable save the offset range
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GPUList[i].minVoltageOffset = values.u.range.min;
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GPUList[i].maxVoltageOffset = values.u.range.max;
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//qDebug() << values.u.range.min << values.u.range.max << "offset range";
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} else {
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// Check if it's readable
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if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
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GPUList[i].voltageReadable = true;
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}
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}
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// Query if core clock offset is writable
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ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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GPUList[i].maxPerfMode,
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NV_CTRL_GPU_NVCLOCK_OFFSET,
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&values);
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if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
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GPUList[i].overClockAvailable = true;
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GPUList[i].coreClkReadable = true;
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GPUList[i].minCoreClkOffset = values.u.range.min;
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GPUList[i].maxCoreClkOffset = values.u.range.max;
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//qDebug() << values.u.range.min << values.u.range.max << "offset range";
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} else {
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if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
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GPUList[i].coreClkReadable = true;
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}
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}
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// Query if memory clock offset is writable
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ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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GPUList[i].maxPerfMode,
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NV_CTRL_GPU_MEM_TRANSFER_RATE_OFFSET,
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&values);
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if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
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GPUList[i].memOverClockAvailable = true;
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GPUList[i].memClkReadable = true;
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GPUList[i].minMemClkOffset = values.u.range.min;
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GPUList[i].maxMemClkOffset = values.u.range.max;
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qDebug() << values.u.range.min << values.u.range.max << "offset range";
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} else {
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if ((values.permissions & ATTRIBUTE_TYPE_READ) == ATTRIBUTE_TYPE_READ) {
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GPUList[i].memClkReadable = true;
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}
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}
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// Query if fan control mode is writable
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ret = XNVCTRLQueryValidTargetAttributeValues(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_GPU_COOLER_MANUAL_CONTROL,
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&values);
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if ((values.permissions & ATTRIBUTE_TYPE_WRITE) == ATTRIBUTE_TYPE_WRITE) {
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GPUList[i].manualFanCtrlAvailable = true;
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qDebug() << "fan control available";
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// Query fan control mode
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int retval;
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ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_GPU_COOLER_MANUAL_CONTROL,
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&retval);
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if ((retval & NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE) == NV_CTRL_GPU_COOLER_MANUAL_CONTROL_TRUE) {
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qDebug() << "fanctl on";
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GPUList[i].fanControlMode = 1;
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} else {
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GPUList[i].fanControlMode = 0;
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qDebug() << "fanctl off";
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}
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}
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// Query amount of VRAM
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ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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i,
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0,
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NV_CTRL_TOTAL_DEDICATED_GPU_MEMORY,
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&GPUList[i].totalVRAM);
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qDebug() << GPUList[i].totalVRAM << "vram";
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}
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}
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void nvidia::queryGPUMaxPerfMode(int GPUIndex)
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{
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char* result;
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Bool ret = XNVCTRLQueryTargetStringAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_STRING_PERFORMANCE_MODES,
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&result);
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if(ret){
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QString modes(result);
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free(result);
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// Each perf mode is separated by a ";" symbol, so for obtaining the number
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// of maximal performance mode it should be enough to just count number of
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// ";" occurences
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int maxPerfMode = modes.count(';');
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GPUList[GPUIndex].maxPerfMode = uint(maxPerfMode);
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qDebug() << modes;
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return;
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}
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else {
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GPUList[GPUIndex].maxPerfMode = 3;
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}
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}
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void nvidia::queryGPUVoltage(int GPUIndex)
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{
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Bool ret;
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ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_GPU_CURRENT_CORE_VOLTAGE,
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&GPUList[GPUIndex].voltage);
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if (!ret) {
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qDebug() << "Couldn't query voltage for GPU";
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}
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qDebug() << GPUList[GPUIndex].voltage;
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}
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void nvidia::queryGPUTemp(int GPUIndex)
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{
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qDebug() << GPUList.size();
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Bool ret;
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ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_THERMAL_SENSOR,
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GPUIndex,
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0,
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NV_CTRL_THERMAL_SENSOR_READING,
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&GPUList[GPUIndex].temp);
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if (!ret) {
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qDebug() << "failed to query GPU temperature";
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}
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qDebug() << GPUList[GPUIndex].temp;
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}
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void nvidia::queryGPUFrequencies(int GPUIndex)
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{
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Bool ret;
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int packedInt = 0;
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int mem = 0;
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int core = 0;
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ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_GPU_CURRENT_CLOCK_FREQS,
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&packedInt);
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// The function returns a 32-bit packed integer, GPU Clock is the upper 16 and Memory Clock lower 16
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mem = (packedInt) & 0xFFFF;
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core = (packedInt & (0xFFFF << (32 - 16))) >> (32 - 16);
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qDebug() << GPUList[GPUIndex].coreFreq << "freq" << core << mem;
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GPUList[GPUIndex].coreFreq = core;
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GPUList[GPUIndex].memFreq = mem;
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}
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void nvidia::queryGPUFanSpeed(int GPUIndex)
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{
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Bool ret;
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ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_COOLER,
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GPUIndex,
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0,
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NV_CTRL_THERMAL_COOLER_CURRENT_LEVEL,
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&GPUList[GPUIndex].fanSpeed);
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}
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void nvidia::queryGPUUsedVRAM(int GPUIndex)
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{
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Bool ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_USED_DEDICATED_GPU_MEMORY,
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&GPUList[GPUIndex].usedVRAM);
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if (!ret) {
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qDebug() << "failed to query used VRAM";
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}
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qDebug() << GPUList[GPUIndex].usedVRAM << "usedvram";
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}
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void nvidia::queryGPUFreqOffset(int GPUIndex)
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{
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Bool ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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GPUList[GPUIndex].maxPerfMode,
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NV_CTRL_GPU_NVCLOCK_OFFSET,
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&GPUList[GPUIndex].coreClkOffset);
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}
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void nvidia::queryGPUMemClkOffset(int GPUIndex)
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{
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Bool ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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GPUList[GPUIndex].maxPerfMode,
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NV_CTRL_GPU_MEM_TRANSFER_RATE_OFFSET,
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&GPUList[GPUIndex].memClkOffset);
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}
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void nvidia::queryGPUVoltageOffset(int GPUIndex)
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{
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Bool ret = XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_GPU_OVER_VOLTAGE_OFFSET,
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&GPUList[GPUIndex].voltageOffset);
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qDebug() << GPUList[GPUIndex].voltageOffset << "offset";
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}
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bool nvidia::assignGPUFanSpeed(int GPUIndex, int targetValue)
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{
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Bool ret;
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ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_COOLER,
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GPUIndex,
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0,
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NV_CTRL_THERMAL_COOLER_LEVEL,
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targetValue);
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return ret;
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}
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bool nvidia::assignGPUFanCtlMode(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_GPU_COOLER_MANUAL_CONTROL,
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targetValue);
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return ret;
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}
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bool nvidia::assignGPUFreqOffset(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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GPUList[GPUIndex].maxPerfMode, // This argument is the performance mode
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NV_CTRL_GPU_NVCLOCK_OFFSET,
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targetValue);
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qDebug() << ret << "freqassign";
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return ret;
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}
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bool nvidia::assignGPUMemClockOffset(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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GPUList[GPUIndex].maxPerfMode,
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NV_CTRL_GPU_MEM_TRANSFER_RATE_OFFSET,
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targetValue);
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qDebug() << ret << "memassign";
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return ret;
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}
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bool nvidia::assignGPUVoltageOffset(int GPUIndex, int targetValue)
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{
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Bool ret = XNVCTRLSetTargetAttributeAndGetStatus(dpy,
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NV_CTRL_TARGET_TYPE_GPU,
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GPUIndex,
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0,
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NV_CTRL_GPU_OVER_VOLTAGE_OFFSET,
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targetValue);
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qDebug() << ret;
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return ret;
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}
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/*bool nvidia::setup()
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{
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dpy = XOpenDisplay(nullptr);
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int *temp;
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XNVCTRLQueryTargetAttribute(dpy,
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NV_CTRL_TARGET_TYPE_THERMAL_SENSOR,
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0,
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0,
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NV_CTRL_THERMAL_SENSOR_READING,
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temp);
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qDebug() << temp;
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return true;
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}*/
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bool nvidia::setupNVML(int GPUIndex)
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{
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nvmlDevice_t *dev = new nvmlDevice_t;
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device = dev;
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nvmlReturn_t ret = nvmlInit();
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char name[64];
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nvmlDeviceGetHandleByIndex(GPUIndex, dev);
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//nvmlDeviceGetName(dev, name, sizeof(name)/sizeof(name[0]));
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qDebug() << name << "from nvml";
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if (NVML_SUCCESS != ret) {
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return false;
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}
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//queryGPUUtils(0);
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//queryGPUPowerLimitLimits(0);
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//queryGPUPowerDraw(0);
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//qDebug() << assignGPUPowerLimit(150000);
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return true;
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}
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void nvidia::queryGPUUtils(int GPUIndex)
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{
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nvmlUtilization_t utils;
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nvmlReturn_t ret = nvmlDeviceGetUtilizationRates(*device, &utils);
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if (NVML_SUCCESS != ret) {
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qDebug() << "failed to query GPU utilizations";
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}
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qDebug() << utils.gpu << utils.memory << "utils";
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GPUList[GPUIndex].memUtil = utils.memory;
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GPUList[GPUIndex].coreUtil = utils.gpu;
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}
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void nvidia::queryGPUPowerDraw(int GPUIndex)
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{
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uint usg;
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nvmlReturn_t ret = nvmlDeviceGetPowerUsage(*device, &usg);
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if (NVML_SUCCESS != ret) {
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qDebug() << "failed to query power usage";
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} else {
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GPUList[GPUIndex].powerDraw = usg;
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qDebug() << usg << "pwrusg";
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}
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}
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void nvidia::queryGPUPowerLimitLimits(int GPUIndex)
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{
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uint maxlim;
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uint minlim;
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nvmlReturn_t ret = nvmlDeviceGetPowerManagementLimitConstraints(*device, &minlim, &maxlim);
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if (NVML_SUCCESS != ret) {
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qDebug() << "failed to query power limit constraints";
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} else {
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GPUList[GPUIndex].minPowerLim = minlim;
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GPUList[GPUIndex].maxPowerLim = maxlim;
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qDebug() << minlim << maxlim << "powerlims";
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}
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}
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void nvidia::queryGPUPowerLimit(int GPUIndex)
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{
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uint lim;
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nvmlReturn_t ret = nvmlDeviceGetPowerManagementLimit(*device, &lim);
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if (NVML_SUCCESS != ret) {
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qDebug() << "failed to query power limit";
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} else {
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GPUList[GPUIndex].powerLim = lim;
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}
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}
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void nvidia::queryGPUCurrentMaxClocks(int GPUIndex)
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{
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uint curmax;
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// Query maximum core clock
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nvmlReturn_t ret = nvmlDeviceGetMaxClockInfo(*device, NVML_CLOCK_GRAPHICS, &curmax);
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if (NVML_SUCCESS != ret) {
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qDebug() << "Failed to query maximum core clock";
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} else {
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GPUList[GPUIndex].maxCoreClk = curmax;
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}
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// Query maximum memory clock
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ret = nvmlDeviceGetMaxClockInfo(*device, NVML_CLOCK_MEM, &curmax);
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if (NVML_SUCCESS != ret) {
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qDebug() << "Failed to query maximum memory clock";
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} else {
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GPUList[GPUIndex].maxMemClk = curmax;
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qDebug() << curmax << "current max clock";
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}
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}
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void nvidia::queryGPUPowerLimitAvailability(int GPUIndex)
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{
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// Assign the current power limit to see if modifying it is available
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nvmlReturn_t ret = nvmlDeviceSetPowerManagementLimit(*device, GPUList[GPUIndex].powerLim);
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if (NVML_ERROR_NOT_SUPPORTED == ret) {
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GPUList[GPUIndex].powerLimitAvailable = false;
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} else {
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GPUList[GPUIndex].powerLimitAvailable = true;
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}
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}
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bool nvidia::assignGPUPowerLimit(uint targetValue)
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{
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nvmlReturn_t ret = nvmlDeviceSetPowerManagementLimit(*device, targetValue);
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if (NVML_SUCCESS != ret) {
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return false;
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}
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return true;
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}
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