From 18f12116c09d749944002548a1de635331f31054 Mon Sep 17 00:00:00 2001 From: Sam Demeulemeester Date: Mon, 29 Aug 2022 02:50:11 +0200 Subject: [PATCH] Fix a rare capacity detection issue with DDR3 modules built using 3 or 4 ranks --- system/smbus.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/system/smbus.c b/system/smbus.c index a23ce42..fab647a 100644 --- a/system/smbus.c +++ b/system/smbus.c @@ -523,10 +523,11 @@ static void parse_spd_ddr3(spd_info *spdi, uint8_t slot_idx) spdi->module_size = 1U << ( ((get_spd(slot_idx, 4) & 0xF) + 5) + // Total SDRAM capacity: (256 Mbits << byte4[3:0]) / 1 KB ((get_spd(slot_idx, 8) & 0x7) + 3) - // Primary Bus Width: 8 << byte8[2:0] - ((get_spd(slot_idx, 7) & 0x7) + 2) + // SDRAM Device Width: 4 << byte7[2:0] - ((get_spd(slot_idx, 7) >> 3) & 0x7) // Number of Ranks: byte7[5:3] + ((get_spd(slot_idx, 7) & 0x7) + 2) // SDRAM Device Width: 4 << byte7[2:0] ); + spdi->module_size *= ((get_spd(slot_idx, 7) >> 3) & 0x7) + 1; // Number of Ranks: byte7[5:3] + spdi->hasECC = (((get_spd(slot_idx, 8) >> 3) & 1) == 1); uint8_t tck = get_spd(slot_idx, 12);