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Add config flag (enable_ecc_polling) to toggle ECC polling.

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Currently disabled by default for v7 release
This commit is contained in:
Sam Demeulemeester 2023-11-19 17:01:52 +01:00
parent e5200c9b89
commit 2d92fddd02
3 changed files with 41 additions and 34 deletions
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2
app/config.c
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@ -99,6 +99,8 @@ bool enable_sm = true;
bool enable_bench = true; bool enable_bench = true;
bool enable_mch_read = true; bool enable_mch_read = true;
bool enable_ecc_polling = false;
bool pause_at_start = true; bool pause_at_start = true;
power_save_t power_save = POWER_SAVE_HIGH; power_save_t power_save = POWER_SAVE_HIGH;

1
app/config.h
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@ -59,6 +59,7 @@ extern bool enable_sm;
extern bool enable_tty; extern bool enable_tty;
extern bool enable_bench; extern bool enable_bench;
extern bool enable_mch_read; extern bool enable_mch_read;
extern bool enable_ecc_polling;
extern bool pause_at_start; extern bool pause_at_start;

72
system/imc/amd_zen.c
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@ -8,6 +8,7 @@
#include "error.h" #include "error.h"
#include "config.h"
#include "cpuinfo.h" #include "cpuinfo.h"
#include "memctrl.h" #include "memctrl.h"
#include "msr.h" #include "msr.h"
@ -43,7 +44,6 @@ void get_imc_config_amd_zen(void)
{ {
uint32_t smn_reg, offset; uint32_t smn_reg, offset;
uint32_t reg_cha, reg_chb; uint32_t reg_cha, reg_chb;
uint32_t regl, regh;
imc.tCL_dec = 0; imc.tCL_dec = 0;
@ -92,42 +92,46 @@ void get_imc_config_amd_zen(void)
// Detect ECC (x64 only) // Detect ECC (x64 only)
#if TESTWORD_WIDTH > 32 #if TESTWORD_WIDTH > 32
smn_reg = amd_smn_read(AMD_SMN_UMC_DRAM_ECC_CTRL + offset); if (enable_ecc_polling) {
if (smn_reg & (ECC_RD_EN | ECC_WR_EN)) { uint32_t regl, regh;
ecc_status.ecc_enabled = true;
// Number of UMC to init smn_reg = amd_smn_read(AMD_SMN_UMC_DRAM_ECC_CTRL + offset);
uint8_t umc = 0, umc_max = 0; if (smn_reg & (ECC_RD_EN | ECC_WR_EN)) {
uint32_t umc_banks_bits = 0; ecc_status.ecc_enabled = true;
if (imc.family == IMC_K19_VRM || imc.family == IMC_K19_RPL) { // Number of UMC to init
umc_max = 4; uint8_t umc = 0, umc_max = 0;
umc_banks_bits = AMD_MCG_CTL_4_BANKS; uint32_t umc_banks_bits = 0;
} else {
umc_max = 2; if (imc.family == IMC_K19_VRM || imc.family == IMC_K19_RPL) {
umc_banks_bits = AMD_MCG_CTL_2_BANKS; umc_max = 4;
umc_banks_bits = AMD_MCG_CTL_4_BANKS;
} else {
umc_max = 2;
umc_banks_bits = AMD_MCG_CTL_2_BANKS;
}
// Enable ECC reporting
rdmsr(MSR_IA32_MCG_CTL, regl, regh);
wrmsr(MSR_IA32_MCG_CTL, regl | umc_banks_bits, regh);
rdmsr(MSR_AMD64_HW_CONF, regl, regh);
wrmsr(MSR_AMD64_HW_CONF, regl | AMD_MCA_STATUS_WR_ENABLE, regh); // // Enable Write to MCA STATUS Register
for (umc = 0; umc < umc_max; umc++)
{
rdmsr(MSR_AMD64_UMC_MCA_CTRL + (umc * AMD_UMC_OFFSET), regl, regh);
wrmsr(MSR_AMD64_UMC_MCA_CTRL + (umc * AMD_UMC_OFFSET), regl | 1, regh);
}
smn_reg = amd_smn_read(AMD_SMN_UMC_ECC_ERR_CNT_SEL);
amd_smn_write(AMD_SMN_UMC_ECC_ERR_CNT_SEL, smn_reg | AMD_UMC_ERR_CNT_EN); // Enable CH0 Error CNT
smn_reg = amd_smn_read(AMD_SMN_UMC_ECC_ERR_CNT_SEL + AMD_SMN_UMC_CHB_OFFSET);
amd_smn_write(AMD_SMN_UMC_ECC_ERR_CNT_SEL + AMD_SMN_UMC_CHB_OFFSET, smn_reg | AMD_UMC_ERR_CNT_EN); // Enable CH1 Error CNT
poll_ecc_amd_zen(false); // Clear ECC registers
} }
// Enable ECC reporting
rdmsr(MSR_IA32_MCG_CTL, regl, regh);
wrmsr(MSR_IA32_MCG_CTL, regl | umc_banks_bits, regh);
rdmsr(MSR_AMD64_HW_CONF, regl, regh);
wrmsr(MSR_AMD64_HW_CONF, regl | AMD_MCA_STATUS_WR_ENABLE, regh); // // Enable Write to MCA STATUS Register
for (umc = 0; umc < umc_max; umc++)
{
rdmsr(MSR_AMD64_UMC_MCA_CTRL + (umc * AMD_UMC_OFFSET), regl, regh);
wrmsr(MSR_AMD64_UMC_MCA_CTRL + (umc * AMD_UMC_OFFSET), regl | 1, regh);
}
smn_reg = amd_smn_read(AMD_SMN_UMC_ECC_ERR_CNT_SEL);
amd_smn_write(AMD_SMN_UMC_ECC_ERR_CNT_SEL, smn_reg | AMD_UMC_ERR_CNT_EN); // Enable CH0 Error CNT
smn_reg = amd_smn_read(AMD_SMN_UMC_ECC_ERR_CNT_SEL + AMD_SMN_UMC_CHB_OFFSET);
amd_smn_write(AMD_SMN_UMC_ECC_ERR_CNT_SEL + AMD_SMN_UMC_CHB_OFFSET, smn_reg | AMD_UMC_ERR_CNT_EN); // Enable CH1 Error CNT
poll_ecc_amd_zen(false); // Clear ECC registers
} }
#endif #endif
} }