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Preliminary ECC support for AMD Zen CPUs (#353)

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* Initial commit for ECC support. Preliminary support for AMD Zen.

* Clear ECC registers at startup

* Add config flag (enable_ecc_polling) to toggle ECC polling. (Currently disabled by default for v7 release)
This commit is contained in:
Sam Demeulemeester
2023-11-29 12:53:05 +01:00
committed by GitHub
parent 9b9c65b968
commit 5dde13b0a1
11 changed files with 286 additions and 35 deletions
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system/imc/amd_zen.c
+136
View File
@@ -6,6 +6,9 @@
// Platform-specific code for AMD Zen CPUs
//
#include "error.h"
#include "config.h"
#include "cpuinfo.h"
#include "memctrl.h"
#include "msr.h"
@@ -13,12 +16,30 @@
#include "imc.h"
#include "display.h" // DEBUG
#define AMD_SMN_UMC_BAR 0x050000
#define AMD_SMN_UMC_CHB_OFFSET 0x100000
#define AMD_SMN_UMC_DRAM_ECC_CTRL AMD_SMN_UMC_BAR + 0x14C
#define AMD_SMN_UMC_DRAM_CONFIG AMD_SMN_UMC_BAR + 0x200
#define AMD_SMN_UMC_DRAM_TIMINGS1 AMD_SMN_UMC_BAR + 0x204
#define AMD_SMN_UMC_DRAM_TIMINGS2 AMD_SMN_UMC_BAR + 0x208
#define AMD_SMN_UMC_ECC_ERR_CNT_SEL AMD_SMN_UMC_BAR + 0xD80
#define AMD_SMN_UMC_ECC_ERR_CNT AMD_SMN_UMC_BAR + 0xD84
#define AMD_UMC_OFFSET 0x10
#define AMD_UMC_VALID_ERROR_BIT (1 << 31)
#define AMD_UMC_ERROR_CECC_BIT (1 << 14)
#define AMD_UMC_ERROR_UECC_BIT (1 << 13)
#define AMD_UMC_ERR_CNT_EN (1 << 15)
#define AMD_MCG_CTL_2_BANKS (1 << 16) | (1 << 15)
#define AMD_MCG_CTL_4_BANKS (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15)
#define AMD_MCA_STATUS_WR_ENABLE (1 << 18)
#define ECC_RD_EN (1 << 10)
#define ECC_WR_EN (1 << 0)
void get_imc_config_amd_zen(void)
{
uint32_t smn_reg, offset;
@@ -68,4 +89,119 @@ void get_imc_config_amd_zen(void)
// RAS Precharge (tRP)
imc.tRP = (smn_reg >> 16) & 0x3F;
// Detect ECC (x64 only)
#if TESTWORD_WIDTH > 32
if (enable_ecc_polling) {
uint32_t regl, regh;
smn_reg = amd_smn_read(AMD_SMN_UMC_DRAM_ECC_CTRL + offset);
if (smn_reg & (ECC_RD_EN | ECC_WR_EN)) {
ecc_status.ecc_enabled = true;
// Number of UMC to init
uint8_t umc = 0, umc_max = 0;
uint32_t umc_banks_bits = 0;
if (imc.family == IMC_K19_VRM || imc.family == IMC_K19_RPL) {
umc_max = 4;
umc_banks_bits = AMD_MCG_CTL_4_BANKS;
} else {
umc_max = 2;
umc_banks_bits = AMD_MCG_CTL_2_BANKS;
}
// Enable ECC reporting
rdmsr(MSR_IA32_MCG_CTL, regl, regh);
wrmsr(MSR_IA32_MCG_CTL, regl | umc_banks_bits, regh);
rdmsr(MSR_AMD64_HW_CONF, regl, regh);
wrmsr(MSR_AMD64_HW_CONF, regl | AMD_MCA_STATUS_WR_ENABLE, regh); // // Enable Write to MCA STATUS Register
for (umc = 0; umc < umc_max; umc++)
{
rdmsr(MSR_AMD64_UMC_MCA_CTRL + (umc * AMD_UMC_OFFSET), regl, regh);
wrmsr(MSR_AMD64_UMC_MCA_CTRL + (umc * AMD_UMC_OFFSET), regl | 1, regh);
}
smn_reg = amd_smn_read(AMD_SMN_UMC_ECC_ERR_CNT_SEL);
amd_smn_write(AMD_SMN_UMC_ECC_ERR_CNT_SEL, smn_reg | AMD_UMC_ERR_CNT_EN); // Enable CH0 Error CNT
smn_reg = amd_smn_read(AMD_SMN_UMC_ECC_ERR_CNT_SEL + AMD_SMN_UMC_CHB_OFFSET);
amd_smn_write(AMD_SMN_UMC_ECC_ERR_CNT_SEL + AMD_SMN_UMC_CHB_OFFSET, smn_reg | AMD_UMC_ERR_CNT_EN); // Enable CH1 Error CNT
poll_ecc_amd_zen(false); // Clear ECC registers
}
}
#endif
}
void poll_ecc_amd_zen(bool report)
{
uint8_t umc = 0, umc_max = 0;
uint32_t regh, regl;
// Number of UMC to check
if (imc.family == IMC_K19_VRM || imc.family == IMC_K19_RPL) {
umc_max = 4;
} else {
umc_max = 2;
}
// Check all UMCs
for (umc = 0; umc < umc_max; umc++)
{
// Get Status Register
rdmsr(MSR_AMD64_UMC_MCA_STATUS + (AMD_UMC_OFFSET * umc), regl, regh);
// Check if ECC error happened
if (regh & AMD_UMC_VALID_ERROR_BIT) {
// Check the type or error. Currently, we only report Corrected ECC error
// Uncorrected ECC errors are skipped to avoid double detection
if (regh & AMD_UMC_ERROR_CECC_BIT) {
ecc_status.type = ECC_ERR_CORRECTED;
} else if (regh & AMD_UMC_ERROR_UECC_BIT) {
ecc_status.type = ECC_ERR_UNCORRECTED;
} else {
ecc_status.type = ERR_UNKNOWN;
}
// Populate Channel Number
ecc_status.channel = umc;
// Get Core# associated with the error
ecc_status.core = regh & 0x3F;
// Get address
rdmsr(MSR_AMD64_UMC_MCA_ADDR + (AMD_UMC_OFFSET * umc), regl, regh);
ecc_status.addr = (uint64_t)(regh & 0x00FFFFFF) << 32;
ecc_status.addr |= regl;
// Clear Address n-th LSBs according to MSR bit[61:56]
ecc_status.addr &= ~0ULL << ((regh >> 24) & 0x3F);
// Get ECC Error Count
ecc_status.count = amd_smn_read(AMD_SMN_UMC_ECC_ERR_CNT + (AMD_SMN_UMC_CHB_OFFSET * umc)) & 0xFFFF;
if (!ecc_status.count) ecc_status.count++;
// Report error
if (report) {
ecc_error();
}
// Clear Error
rdmsr(MSR_AMD64_UMC_MCA_STATUS + (AMD_UMC_OFFSET * umc), regl, regh);
wrmsr(MSR_AMD64_UMC_MCA_STATUS + (AMD_UMC_OFFSET * umc), regl, regh & ~AMD_UMC_VALID_ERROR_BIT);
amd_smn_write(AMD_SMN_UMC_ECC_ERR_CNT + (AMD_SMN_UMC_CHB_OFFSET * umc), 0x0);
// Clear Internal ECC Error status
ecc_status.type = ECC_ERR_NONE;
ecc_status.addr = 0;
ecc_status.count = 0;
ecc_status.core = 0;
ecc_status.channel = 0;
}
}
}
system/imc/imc.h
+11
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@@ -3,6 +3,10 @@
#ifndef _IMC_H_
#define _IMC_H_
/**
* Integrated Memory Controler (IMC) Settings Detection Code
*/
/* Memory configuration Detection for AMD Zen CPUs */
void get_imc_config_amd_zen(void);
@@ -21,4 +25,11 @@ void get_imc_config_intel_icl(void);
/* Memory configuration Detection for Intel Alder Lake */
void get_imc_config_intel_adl(void);
/**
* ECC Polling Code for various IMCs
*/
/* ECC Polling Code for AMD Zen CPUs */
void poll_ecc_amd_zen(bool report);
#endif /* _IMC_H_ */
system/memctrl.c
+21 -1
View File
@@ -14,9 +14,11 @@
#include "memctrl.h"
#include "imc/imc.h"
#include "display.h"
imc_info_t imc = {"UNDEF", 0, 0, 0, 0, 0, 0, 0, 0};
ecc_info_t ecc_status = {false, ECC_ERR_NONE, 0, 0, 0, 0, 0};
ecc_info_t ecc_status = {false, ECC_ERR_NONE, 0, 0, 0, 0};
// ---------------------
// -- Public function --
@@ -64,3 +66,21 @@ void memctrl_init(void)
imc.freq = 0;
}
}
void memctrl_poll_ecc(void)
{
if (!ecc_status.ecc_enabled) {
return;
}
switch(imc.family) {
case IMC_K17:
case IMC_K19_VRM:
case IMC_K19_RPL:
case IMC_K19_RBT:
poll_ecc_amd_zen(true);
break;
default:
break;
}
}
system/memctrl.h
+9 -7
View File
@@ -27,17 +27,17 @@ typedef struct __attribute__((packed)) imc_infos {
typedef enum {
ECC_ERR_NONE,
ECC_ERR_CORRECTED,
ECC_ERR_UNCORRECTED
ECC_ERR_UNCORRECTED,
ERR_UNKNOWN
} ecc_error_type_t;
typedef struct __attribute__((packed)) ecc_status {
bool ecc_enabled;
ecc_error_type_t err_type;
uint64_t err_adr;
uint32_t err_col;
uint32_t err_row;
uint32_t err_rank;
uint32_t err_bank;
ecc_error_type_t type;
uint64_t addr;
uint32_t count;
uint16_t core;
uint8_t channel;
} ecc_info_t;
/**
@@ -54,4 +54,6 @@ extern ecc_info_t ecc_status;
void memctrl_init(void);
void memctrl_poll_ecc(void);
#endif // MEMCTRL_H
system/msr.h
+5
View File
@@ -8,6 +8,7 @@
*
*//*
* Copyright (C) 2020-2022 Martin Whitaker.
* Copyright (C) 2020-2023 Sam Demeulemeester.
*/
#define MSR_PLATFORM_INFO 0xce
@@ -30,6 +31,10 @@
#define MSR_AMD64_NB_CFG 0xc001001f
#define MSR_AMD64_COFVID_STATUS 0xc0010071
#define MSR_AMD64_UMC_MCA_CTRL 0xc00020f0
#define MSR_AMD64_UMC_MCA_STATUS 0xc00020f1
#define MSR_AMD64_UMC_MCA_ADDR 0xc00020f2
#define MSR_AMD64_HW_CONF 0xc0010015
#define MSR_VIA_TEMP_C7 0x1169
#define MSR_VIA_TEMP_NANO 0x1423