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https://github.com/memtest86plus/memtest86plus.git
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WIP BROKEN NX enablement, for now only for the second page directory.
TODO:
* selective NX enablement on pd0, pd1 and pd3.
Unconditional NX on the whole pd3 makes memtest86+ reboot in a QEMU-emulated computer.
* if supported on all x86_64 CPUs, simply enable long mode and NX simultaneously ? A real K8 dual-core processor didn't seem to hate it, at least.
* startup code: NX enablement for x86, on capable computers (CPUID 0x80000001, edx bit 20).
* set the appropriate flag in the headers.
This commit is contained in:
Lionel Debroux
parent
a541469850
commit
61afe1143b
@ -104,6 +104,7 @@ startup:
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movl %esi, boot_params_addr@GOTOFF(%ebx)
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# ...and check if the processor supports long mode.
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# TODO and NX
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movl $0x80000000, %eax # check if function 0x80000001 is available
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pushl %ebx # ebx is overwritten by cpuid
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@ -206,7 +207,7 @@ init_idt_descr:
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jz 1f # bail if not supported
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movl %cr4, %eax # enable PAE
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orl $0x00000020, %eax
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orb $0x20, %al
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movl %eax, %cr4
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leal pdp@GOTOFF(%ebx), %eax # set the page directory base address
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@ -219,7 +220,7 @@ init_idt_descr:
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movl $0xc0000080, %ecx # enable long mode
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rdmsr
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orl $0x00000100, %eax
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orb $0x01, %ah
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wrmsr
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leal pml4@GOTOFF(%ebx), %eax # set the page directory base address
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@ -648,17 +649,17 @@ gdt_end:
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.data
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.macro ptes64 start, count=64
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.quad \start + 0x0000000 + 0x83
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.quad \start + 0x0200000 + 0x83
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.quad \start + 0x0400000 + 0x83
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.quad \start + 0x0600000 + 0x83
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.quad \start + 0x0800000 + 0x83
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.quad \start + 0x0A00000 + 0x83
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.quad \start + 0x0C00000 + 0x83
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.quad \start + 0x0E00000 + 0x83
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.macro ptes64 start, flags, count=64
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.quad \start + 0x0000000 + \flags
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.quad \start + 0x0200000 + \flags
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.quad \start + 0x0400000 + \flags
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.quad \start + 0x0600000 + \flags
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.quad \start + 0x0800000 + \flags
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.quad \start + 0x0A00000 + \flags
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.quad \start + 0x0C00000 + \flags
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.quad \start + 0x0E00000 + \flags
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.if \count-1
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ptes64 "(\start+0x01000000)",\count-1
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ptes64 "(\start+0x01000000)", \flags, \count-1
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.endif
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.endm
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@ -702,22 +703,22 @@ pdp:
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.align 4096
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.globl pd0
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pd0:
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ptes64 0x0000000000000000
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ptes64 0x0000000000000000,0x0000000000000083
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.align 4096
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.globl pd1
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pd1:
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ptes64 0x0000000040000000
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ptes64 0x0000000040000000,0x0000000000000083
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.align 4096
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.globl pd2
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pd2:
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ptes64 0x0000000080000000
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ptes64 0x0000000080000000,0x0000000000000083
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.align 4096
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.globl pd3
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pd3:
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ptes64 0x00000000C0000000
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ptes64 0x00000000C0000000,0x0000000000000083
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.previous
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@ -71,14 +71,14 @@ startup32:
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# Enable PAE.
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movl %cr4, %eax
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orl $0x20, %eax
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orb $0x20, %al
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movl %eax, %cr4
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# Enable long mode.
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movl $0xc0000080, %ecx
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rdmsr
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orl $0x00000100, %eax
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orb $0x01, %ah
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wrmsr
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# Enable paging and protection.
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@ -162,6 +162,13 @@ startup:
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leaq _stacks(%rip), %rsp
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addq %rax, %rsp
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# Enable NX.
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movl $0xc0000080, %ecx
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rdmsr
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orb $0x08, %ah
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wrmsr
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# Initialise the pml4 and pdp tables.
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leaq pml4(%rip), %rcx
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@ -255,8 +262,8 @@ flush: movw $KERNEL_DS, %ax
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# Enable SSE.
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movq %cr0, %rax
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andw $0xfffb, %ax # clear coprocessor emulation bit
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orw $0x0002, %ax # set coprocessor monitoring bit
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andb $0xfb, %al # clear coprocessor emulation bit
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orb $0x02, %al # set coprocessor monitoring bit
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mov %rax, %cr0
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movq %cr4, %rax
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orw $0x0600, %ax # set OSFXSR and OSXMMEXCPT
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@ -465,17 +472,17 @@ gdt_end:
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.data
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.macro ptes64 start, count=64
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.quad \start + 0x0000000 + 0x83
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.quad \start + 0x0200000 + 0x83
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.quad \start + 0x0400000 + 0x83
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.quad \start + 0x0600000 + 0x83
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.quad \start + 0x0800000 + 0x83
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.quad \start + 0x0A00000 + 0x83
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.quad \start + 0x0C00000 + 0x83
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.quad \start + 0x0E00000 + 0x83
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.macro ptes64 start, flags, count=64
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.quad \start + 0x0000000 + \flags
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.quad \start + 0x0200000 + \flags
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.quad \start + 0x0400000 + \flags
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.quad \start + 0x0600000 + \flags
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.quad \start + 0x0800000 + \flags
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.quad \start + 0x0A00000 + \flags
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.quad \start + 0x0C00000 + \flags
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.quad \start + 0x0E00000 + \flags
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.if \count-1
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ptes64 "(\start+0x01000000)",\count-1
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ptes64 "(\start+0x01000000)", \flags, \count-1
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.endif
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.endm
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@ -514,22 +521,22 @@ pdp:
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.align 4096
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.globl pd0
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pd0:
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ptes64 0x0000000000000000
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ptes64 0x0000000000000000,0x0000000000000083
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.align 4096
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.globl pd1
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pd1:
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ptes64 0x0000000040000000
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ptes64 0x0000000040000000,0x0000000000000083
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.align 4096
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.globl pd2
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pd2:
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ptes64 0x0000000080000000
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ptes64 0x0000000080000000,0x8000000000000083
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.align 4096
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.globl pd3
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pd3:
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ptes64 0x00000000C0000000
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ptes64 0x00000000C0000000,0x0000000000000083
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.previous
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@ -567,14 +574,14 @@ data32 lgdt ap_gdt_descr - ap_trampoline
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# Enable PAE.
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movl %cr4, %eax
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orl $0x20, %eax
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orb $0x20, %al
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movl %eax, %cr4
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# Enable long mode.
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movl $0xc0000080, %ecx
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rdmsr
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orl $0x00000100, %eax
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orb $0x01, %ah
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wrmsr
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# Enable paging and protection.
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@ -583,6 +590,13 @@ data32 lgdt ap_gdt_descr - ap_trampoline
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orl $0x80000001, %eax
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movl %eax, %cr0
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# Enable NX.
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movl $0xc0000080, %ecx
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rdmsr
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orb $0x08, %ah
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wrmsr
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# Jump to the 64-bit entry point.
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ap_jump:
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data32 ljmp $KERNEL_CS, $0
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@ -100,7 +100,9 @@ typedef union {
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uint32_t : 12; // ECX feature flags, bit 20
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uint32_t x2apic : 1;
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uint32_t : 10; // ECX feature flags, bit 31
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uint32_t : 29; // EDX extended feature flags, bit 0
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uint32_t : 19; // EDX extended feature flags, bit 0
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uint32_t nx : 1;
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uint32_t : 9;
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uint32_t lm : 1;
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uint32_t : 2; // EDX extended feature flags, bit 31
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};
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@ -125,13 +125,14 @@ bool map_window(uintptr_t start_page)
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return false;
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}
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if (cpuid_info.flags.lm == 0 && (start_page >= PAGE_C(64,GB))) {
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// Fail, we want an address that is out of bounds
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// for PAE and no long mode (ie. 32 bit CPU).
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// Fail, we want an address that is out of bounds
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// for PAE and no long mode (ie. 32 bit CPU).
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return false;
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}
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// Compute the page table entries.
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uint64_t flags = cpuid_info.flags.nx ? UINT64_C(0x8000000000000083) : 0x83;
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for (uintptr_t i = 0; i < 512; i++) {
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pd2[i] = ((uint64_t)window << 30) + (i << VM_PAGE_SHIFT) + 0x83;
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pd2[i] = ((uint64_t)window << 30) + (i << VM_PAGE_SHIFT) + flags;
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}
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// Reload the PDBR to flush any remnants of the old mapping.
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load_pdbr();
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