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Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs (#259)

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* Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs

Use extended CPUID for VIA C3/C7/Nano cache information.

Use MSR reads for Nano/Zhaoxin and VIA C7 processor temperature.

Tested on VIA C7-D 1.5GHz.

* Small code conventions fixes

* Fix overallocation of cpuid_cache_info_t union (From PR #263)

---------

Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
This commit is contained in:
Jonathan Teh
2023-02-10 21:32:31 +00:00
committed by GitHub
parent a47f681151
commit 8305d47675
4 changed files with 48 additions and 4 deletions
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20
system/cpuid.c
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@@ -128,6 +128,26 @@ void cpuid_init(void)
);
}
break;
case 'C':
if (cpuid_info.vendor_id.str[5] == 'I') break; // Cyrix
// VIA / CentaurHauls
if (cpuid_info.max_xcpuid >= 0x80000005) {
cpuid(0x80000005, 0,
&reg[0],
&reg[1],
&cpuid_info.cache_info.raw[0],
&cpuid_info.cache_info.raw[1]
);
}
if (cpuid_info.max_xcpuid >= 0x80000006) {
cpuid(0x80000006, 0,
&reg[0],
&reg[1],
&cpuid_info.cache_info.raw[2],
&cpuid_info.cache_info.raw[3]
);
}
break;
case 'G':
// Intel Processors
// No cpuid info to read.