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Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs (#259)

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* Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs

Use extended CPUID for VIA C3/C7/Nano cache information.

Use MSR reads for Nano/Zhaoxin and VIA C7 processor temperature.

Tested on VIA C7-D 1.5GHz.

* Small code conventions fixes

* Fix overallocation of cpuid_cache_info_t union (From PR #263)

---------

Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
This commit is contained in:
Jonathan Teh 2023-02-10 21:32:31 +00:00 committed by GitHub
parent a47f681151
commit 8305d47675
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 48 additions and 4 deletions
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20
system/cpuid.c
View File

@ -128,6 +128,26 @@ void cpuid_init(void)
); );
} }
break; break;
case 'C':
if (cpuid_info.vendor_id.str[5] == 'I') break; // Cyrix
// VIA / CentaurHauls
if (cpuid_info.max_xcpuid >= 0x80000005) {
cpuid(0x80000005, 0,
&reg[0],
&reg[1],
&cpuid_info.cache_info.raw[0],
&cpuid_info.cache_info.raw[1]
);
}
if (cpuid_info.max_xcpuid >= 0x80000006) {
cpuid(0x80000006, 0,
&reg[0],
&reg[1],
&cpuid_info.cache_info.raw[2],
&cpuid_info.cache_info.raw[3]
);
}
break;
case 'G': case 'G':
// Intel Processors // Intel Processors
// No cpuid info to read. // No cpuid info to read.

2
system/cpuid.h
View File

@ -122,7 +122,7 @@ typedef union {
} cpuid_brand_string_t; } cpuid_brand_string_t;
typedef union { typedef union {
uint32_t raw[12]; uint32_t raw[4];
struct { struct {
uint32_t : 24; uint32_t : 24;
uint32_t l1_i_size : 8; uint32_t l1_i_size : 8;

10
system/cpuinfo.c
View File

@ -71,10 +71,16 @@ static void determine_cache_size()
l3_cache *= 512; l3_cache *= 512;
break; break;
case 'C': case 'C':
// Zhaoxin CPU only if (cpuid_info.vendor_id.str[5] == 'I') break; // Cyrix
if (cpuid_info.version.family != 7) { // VIA C3/C7/Nano
if (cpuid_info.version.family == 6) {
l1_cache = cpuid_info.cache_info.l1_d_size;
l2_cache = cpuid_info.cache_info.l2_size;
break;
} else if (cpuid_info.version.family != 7) {
break; break;
} }
// Zhaoxin CPU only
/* fall through */ /* fall through */
case 'G': case 'G':
// Intel Processors // Intel Processors

20
system/temperature.c
View File

@ -47,7 +47,7 @@ int get_cpu_temperature(void)
} }
// AMD CPU // AMD CPU
if (cpuid_info.vendor_id.str[0] == 'A' && cpuid_info.version.extendedFamily > 0 && cpuid_info.version.extendedFamily < 8) { else if (cpuid_info.vendor_id.str[0] == 'A' && cpuid_info.version.extendedFamily > 0 && cpuid_info.version.extendedFamily < 8) {
// Untested yet // Untested yet
uint32_t rtcr = pci_config_read32(0, 24, 3, 0xA4); uint32_t rtcr = pci_config_read32(0, 24, 3, 0xA4);
@ -69,5 +69,23 @@ int get_cpu_temperature(void)
return offset + 0.125f * (float)((tval >> 21) & 0x7FF); return offset + 0.125f * (float)((tval >> 21) & 0x7FF);
} }
// VIA/Centaur/Zhaoxin CPU
else if (cpuid_info.vendor_id.str[0] == 'C' && cpuid_info.vendor_id.str[1] == 'e'
&& (cpuid_info.version.family == 6 || cpuid_info.version.family == 7)) {
uint32_t msrl, msrh, msr_temp;
if (cpuid_info.version.family == 7 || cpuid_info.version.model == 0xF) {
msr_temp = 0x1423; // Zhaoxin, Nano
} else if (cpuid_info.version.model == 0xA || cpuid_info.version.model == 0xD) {
msr_temp = 0x1169; // C7 A/D
} else {
return 0;
}
rdmsr(msr_temp, msrl, msrh);
return (int)(msrl & 0xffffff);
}
return 0; return 0;
} }