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Add support for MMIO UART console (#300)

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8/16/32-bit MMIO supported, with configuration options as kernel parameters.
This commit is contained in:
Sam Demeulemeester
2023-05-12 15:49:00 +02:00
committed by GitHub
parent acea409a51
commit 9e3958714b
7 changed files with 101 additions and 24 deletions
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system/serial.c
+20 -6
View File
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2004-2022 Sam Demeulemeester
// Copyright (C) 2004-2023 Sam Demeulemeester
#include <stdbool.h>
#include <stddef.h>
@@ -101,13 +101,21 @@ void tty_init(void)
unsigned char lcr;
console_serial.enable = true;
console_serial.is_mmio = false;
console_serial.base_addr = tty_address;
console_serial.baudrate = tty_baud_rate;
console_serial.parity = SERIAL_DEFAULT_PARITY;
console_serial.bits = SERIAL_DEFAULT_BITS;
console_serial.baudrate = tty_params_baud;
console_serial.reg_width = 1;
console_serial.refclk = UART_REF_CLK;
console_serial.base_addr = serial_base_ports[tty_params_port];
// UART MMIO Address is usually above TOLUD and never < 1MB
if (console_serial.base_addr > 0xFFFF) {
console_serial.is_mmio = true;
console_serial.reg_width = tty_mmio_stride;
console_serial.refclk = tty_mmio_ref_clk;
} else {
console_serial.is_mmio = false;
console_serial.reg_width = 1;
console_serial.refclk = UART_REF_CLK_IO;
}
/* read the Divisor Latch */
uart_status = serial_read_reg(&console_serial, UART_LCR);
@@ -130,6 +138,12 @@ void tty_init(void)
uart_status = serial_read_reg(&console_serial, UART_RX); /* COM? RBR */
serial_write_reg(&console_serial, UART_IER, 0x00); /* Disable all interrupts */
/* In case of MMIO UART, set up FIFO Reg */
if (console_serial.is_mmio) {
serial_write_reg(&console_serial, UART_FCR, 0x00);
serial_write_reg(&console_serial, UART_FCR, (0xFF) & (UART_FCR_ENA | UART_FCR_THR));
}
tty_clear_screen();
tty_disable_cursor();
}
system/serial.h
+10 -4
View File
@@ -7,10 +7,9 @@
* display via Serial/UART.
*
*//*
* Copyright (C) 2004-2022 Sam Demeulemeester.
* Copyright (C) 2004-2023 Sam Demeulemeester.
*/
#define SERIAL_DEFAULT_BAUDRATE 115200
#define SERIAL_DEFAULT_BITS 8
#define SERIAL_DEFAULT_PARITY 0
@@ -19,7 +18,7 @@
#define SERIAL_PORT_0x3E8 2
#define SERIAL_PORT_0x2E8 3
static const uint16_t serial_base_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const uint16_t serial_io_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
struct serial_port {
bool enable;
@@ -49,7 +48,8 @@ struct serial_port {
* Definitions for the Base UART Registers
*/
#define UART_REF_CLK 1843200
#define UART_REF_CLK_IO 1843200
#define UART_REF_CLK_MMIO 48000000
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
@@ -103,6 +103,12 @@ struct serial_port {
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
/*
* Definitions for the FIFO Control Register
*/
#define UART_FCR_ENA 0x01 /* FIFO Enable */
#define UART_FCR_THR 0x20 /* FIFO Threshold */
/*
* Definitions for the Interrupt Enable Register
*/