NuKVM/memtest86plus
3
0
Fork 0
mirror of https://github.com/memtest86plus/memtest86plus.git synced 2025-02-25 18:55:23 -06:00
Code Issues Packages Projects Releases Wiki Activity

Add support for DDR5 in smbus.c. Major rework of various related functions (#2)

Browse Source
This commit is contained in:
Sam Demeulemeester
2022-03-24 03:20:29 +01:00
parent 8e35753ce8
commit b22c032b5a
2 changed files with 243 additions and 127 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
system/smbus.h
View File

@@ -10,6 +10,9 @@
* Copyright (C) 2004-2022 Samuel Demeulemeester.
*/
#define I2C_WRITE 0
#define I2C_READ 1
/* i801 Hosts Addresses */
#define SMBHSTSTS smbusbase
#define SMBHSTCNT smbusbase + 2
@@ -20,7 +23,7 @@
#define SMBBLKDAT smbusbase + 7
#define SMBPEC smbusbase + 8
#define SMBAUXSTS smbusbase + 12
#define SMBAUXCTL smbusbase + 12
#define SMBAUXCTL smbusbase + 13
/* i801 Hosts Status register bits */
#define SMBHSTSTS_BYTE_DONE 0x80
@@ -32,27 +35,23 @@
#define SMBHSTSTS_INTR 0x02
#define SMBHSTSTS_HOST_BUSY 0x01
#define SMBHSTCNT_QUICK 0x00
#define SMBHSTCNT_BYTE 0x04
#define SMBHSTCNT_BYTE_DATA 0x08
#define SMBHSTCNT_WORD_DATA 0x0C
#define SMBHSTCNT_START 0x40
#define SMBHSTCNT_QUICK 0x00
#define SMBHSTCNT_BYTE 0x04
#define SMBHSTCNT_BYTE_DATA 0x08
#define SMBHSTCNT_WORD_DATA 0x0C
#define SMBHSTCNT_BLOCK_DATA 0x14
#define SMBHSTCNT_I2C_BLOCK_DATA 0x18
#define SMBHSTCNT_LAST_BYTE 0x20
#define SMBHSTCNT_START 0x40
/* Platform Capabilities */
#define HAS_SDR (1 << 1)
#define HAS_DDR (1 << 2)
#define HAS_DDR2 (1 << 3)
#define HAS_DDR3 (1 << 4)
#define HAS_DDR4 (1 << 5)
#define HAS_DDR5 (1 << 6)
#define SPD5_MR11 11
struct pci_smbus_controller{
unsigned vendor;
unsigned device;
char *name;
void (*get_adr)(uint8_t idx);
void (*get_adr)(void);
uint8_t (*read_spd_byte)(uint8_t dimmadr, uint16_t bytenum);
uint8_t cap;
};
typedef struct spd_infos {