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[cpuinfo] Fix old CPUs (P5/P6-class) name and cache info (#267)
* cpuinfo: Fix WinChip and Cyrix/NSC CPU name and cache info Always populate the cache info from extended CPUID, it is not used for Intel CPUs, even though it is present, and is useful for non-Intel CPUs. Fix the CPU name and cache sizes for Centaur and Cyrix/NSC CPUs without brand string, which are the WinChip C6 and all Cyrix CPUs except the Media GXm. For the Media GXm and Geode GXm/GXLV/GX1, which are available with both Cyrix and NSC vendor strings, hardcode the L1 cache size. The Geode GX2 uses standard cache info. * Add 'Intel' in CPU names for older CPUs * Add 'Transmeta' and 'IDT' in CPU names for older CPUs ------- Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
This commit is contained in:
Jonathan Teh
GitHub
parent
262aac4f85
commit
dcca756e48
@ -108,50 +108,21 @@ void cpuid_init(void)
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}
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// Get cache information.
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switch (cpuid_info.vendor_id.str[0]) {
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case 'A':
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// AMD Processors
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if (cpuid_info.max_xcpuid >= 0x80000005) {
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cpuid(0x80000005, 0,
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®[0],
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®[1],
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&cpuid_info.cache_info.raw[0],
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&cpuid_info.cache_info.raw[1]
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);
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}
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if (cpuid_info.max_xcpuid >= 0x80000006) {
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cpuid(0x80000006, 0,
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®[0],
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®[1],
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&cpuid_info.cache_info.raw[2],
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&cpuid_info.cache_info.raw[3]
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);
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}
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break;
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case 'C':
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if (cpuid_info.vendor_id.str[5] == 'I') break; // Cyrix
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// VIA / CentaurHauls
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if (cpuid_info.max_xcpuid >= 0x80000005) {
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cpuid(0x80000005, 0,
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®[0],
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®[1],
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&cpuid_info.cache_info.raw[0],
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&cpuid_info.cache_info.raw[1]
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);
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}
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if (cpuid_info.max_xcpuid >= 0x80000006) {
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cpuid(0x80000006, 0,
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®[0],
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®[1],
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&cpuid_info.cache_info.raw[2],
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&cpuid_info.cache_info.raw[3]
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);
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}
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break;
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case 'G':
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// Intel Processors
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// No cpuid info to read.
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break;
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if (cpuid_info.max_xcpuid >= 0x80000005) {
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cpuid(0x80000005, 0,
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®[0],
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®[1],
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&cpuid_info.cache_info.raw[0],
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&cpuid_info.cache_info.raw[1]
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);
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}
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if (cpuid_info.max_xcpuid >= 0x80000006) {
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cpuid(0x80000006, 0,
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®[0],
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®[1],
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&cpuid_info.cache_info.raw[2],
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&cpuid_info.cache_info.raw[3]
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);
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}
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// Detect CPU Topology (Core/Thread) infos
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155
system/cpuinfo.c
155
system/cpuinfo.c
@ -71,9 +71,17 @@ static void determine_cache_size()
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l3_cache *= 512;
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break;
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case 'C':
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if (cpuid_info.vendor_id.str[5] == 'I') break; // Cyrix
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// VIA C3/C7/Nano
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if (cpuid_info.version.family == 6) {
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if (cpuid_info.vendor_id.str[5] == 'I') {
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// Cyrix
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if (cpuid_info.version.family == 5 && cpuid_info.version.model == 4) {
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// Media GXm, Geode GXm/GXLV/GX1
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// Cache info in CPUID has a Cyrix-specific encoding so hardcode it
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l1_cache = 16;
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}
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break;
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}
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// WinChip 2/3, VIA C3/C7/Nano
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if (cpuid_info.version.family == 5 || cpuid_info.version.family == 6) {
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l1_cache = cpuid_info.cache_info.l1_d_size;
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l2_cache = cpuid_info.cache_info.l2_size;
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break;
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@ -83,6 +91,25 @@ static void determine_cache_size()
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// Zhaoxin CPU only
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/* fall through */
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case 'G':
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if (cpuid_info.vendor_id.str[9] == 'N') {
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// National Semiconductor
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if (cpuid_info.version.family == 5) {
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switch (cpuid_info.version.model) {
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case 4:
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// Geode GXm/GXLV/GX1
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// Cache info in CPUID has a Cyrix-specific encoding so hardcode it
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l1_cache = 16;
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break;
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case 5:
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// Geode GX2
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l1_cache = cpuid_info.cache_info.l1_d_size;
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break;
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default:
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break;
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}
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}
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break;
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}
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// Intel Processors
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l1_cache = 0;
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l2_cache = 0;
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@ -605,9 +632,9 @@ static void determine_cpu_model(void)
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// Transmeta Processors - vendor_id starts with "GenuineTMx86"
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if (cpuid_info.vendor_id.str[7] == 'T' ) {
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if (cpuid_info.version.family == 5) {
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cpu_model = "TM 5x00";
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cpu_model = "Transmeta TM 5x00";
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} else if (cpuid_info.version.family == 15) {
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cpu_model = "TM 8x00";
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cpu_model = "Transmeta TM 8x00";
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}
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l1_cache = cpuid_info.cache_info.l1_i_size + cpuid_info.cache_info.l1_d_size;
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l2_cache = cpuid_info.cache_info.l2_size;
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@ -653,14 +680,14 @@ static void determine_cpu_model(void)
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case 2:
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case 3:
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case 7:
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cpu_model = "Pentium";
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cpu_model = "Intel Pentium";
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if (l1_cache == 0) {
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l1_cache = 8;
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}
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break;
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case 4:
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case 8:
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cpu_model = "Pentium-MMX";
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cpu_model = "Intel Pentium MMX";
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if (l1_cache == 0) {
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l1_cache = 16;
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}
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@ -673,54 +700,54 @@ static void determine_cpu_model(void)
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switch (cpuid_info.version.model) {
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case 0:
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case 1:
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cpu_model = "Pentium Pro";
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cpu_model = "Intel Pentium Pro";
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break;
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case 3:
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case 4:
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cpu_model = "Pentium II";
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cpu_model = "Intel Pentium II";
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break;
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case 5:
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if (l2_cache == 0) {
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cpu_model = "Celeron";
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cpu_model = "Intel Celeron";
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} else {
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cpu_model = "Pentium II";
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cpu_model = "Intel Pentium II";
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}
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break;
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case 6:
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if (l2_cache == 128) {
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cpu_model = "Celeron";
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cpu_model = "Intel Celeron";
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} else {
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cpu_model = "Pentium II";
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cpu_model = "Intel Pentium II";
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}
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break;
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case 7:
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case 8:
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case 11:
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if (l2_cache == 128) {
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cpu_model = "Celeron";
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cpu_model = "Intel Celeron";
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} else {
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cpu_model = "Pentium III";
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cpu_model = "Intel Pentium III";
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}
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break;
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case 9:
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if (l2_cache == 512) {
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cpu_model = "Celeron M (0.13)";
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cpu_model = "Intel Celeron M (0.13)";
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} else {
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cpu_model = "Pentium M (0.13)";
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cpu_model = "Intel Pentium M (0.13)";
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}
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break;
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case 10:
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cpu_model = "Pentium III Xeon";
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cpu_model = "Intel Pentium III Xeon";
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break;
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case 12:
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l1_cache = 24;
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cpu_model = "Atom (0.045)";
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cpu_model = "Intel Atom (0.045)";
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break;
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case 13:
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if (l2_cache == 1024) {
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cpu_model = "Celeron M (0.09)";
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cpu_model = "Intel Celeron M (0.09)";
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} else {
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cpu_model = "Pentium M (0.09)";
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cpu_model = "Intel Pentium M (0.09)";
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}
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break;
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case 14:
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@ -728,7 +755,7 @@ static void determine_cpu_model(void)
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break;
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case 15:
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if (l2_cache == 1024) {
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cpu_model = "Pentium E";
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cpu_model = "Intel Pentium E";
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} else {
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cpu_model = "Intel Core 2";
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}
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@ -743,17 +770,17 @@ static void determine_cpu_model(void)
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case 1:
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case 2:
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if (l2_cache == 128) {
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cpu_model = "Celeron";
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cpu_model = "Intel Celeron";
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} else {
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cpu_model = "Pentium 4";
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cpu_model = "Intel Pentium 4";
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}
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break;
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case 3:
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case 4:
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if (l2_cache == 256) {
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cpu_model = "Celeron (0.09)";
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cpu_model = "Intel Celeron (0.09)";
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} else {
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cpu_model = "Pentium 4 (0.09)";
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cpu_model = "Intel Pentium 4 (0.09)";
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}
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break;
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case 6:
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@ -773,78 +800,40 @@ static void determine_cpu_model(void)
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// VIA/Cyrix/Centaur Processors with CPUID
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if (cpuid_info.vendor_id.str[1] == 'e' ) {
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// CentaurHauls
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l1_cache = cpuid_info.cache_info.l1_i_size + cpuid_info.cache_info.l1_d_size;
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l2_cache = cpuid_info.cache_info.l2_size >> 8;
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switch (cpuid_info.version.family) {
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case 5:
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cpu_model = "Centaur 5x86";
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cpu_model = "IDT WinChip C6";
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l1_cache = 32;
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// WinChip 2/3 (models 8/9) have brand string
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break;
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case 6: // VIA C3
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switch (cpuid_info.version.model) {
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case 10:
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cpu_model = "VIA C7 (C5J)";
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l1_cache = 64;
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l2_cache = 128;
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break;
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case 13:
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cpu_model = "VIA C7 (C5R)";
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l1_cache = 64;
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l2_cache = 128;
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break;
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case 15:
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cpu_model = "VIA Isaiah (CN)";
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l1_cache = 64;
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l2_cache = 128;
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break;
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default:
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if (cpuid_info.version.stepping < 8) {
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cpu_model = "VIA C3 Samuel2";
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} else {
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cpu_model = "VIA C3 Eden";
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}
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break;
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}
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default:
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// All VIA/Centaur family values >= 6 have brand string
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break;
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}
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} else { /* CyrixInstead */
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switch (cpuid_info.version.family) {
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case 5:
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case 4:
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switch (cpuid_info.version.model) {
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case 0:
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cpu_model = "Cyrix 6x86MX/MII";
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case 2:
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cpu_model = "Cyrix 5x86";
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l1_cache = 16;
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break;
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case 4:
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cpu_model = "Cyrix GXm";
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cpu_model = "Cyrix MediaGX/GXi";
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l1_cache = 16;
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break;
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default:
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break;
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}
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break;
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case 6: // VIA C3
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switch (cpuid_info.version.model) {
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case 6:
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cpu_model = "Cyrix III";
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break;
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case 7:
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if (cpuid_info.version.stepping < 8) {
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cpu_model = "VIA C3 Samuel2";
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} else {
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cpu_model = "VIA C3 Ezra-T";
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}
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break;
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case 8:
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cpu_model = "VIA C3 Ezra-T";
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break;
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case 9:
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cpu_model = "VIA C3 Nehemiah";
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break;
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default:
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break;
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}
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// L1 = L2 = 64 KB from Cyrix III to Nehemiah
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case 5:
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cpu_model = "Cyrix 6x86/6x86L";
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l1_cache = 16;
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// Media GXm (model 4) has brand string
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break;
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case 6:
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cpu_model = "Cyrix 6x86MX/MII";
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l1_cache = 64;
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l2_cache = 64;
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break;
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default:
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break;
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@ -855,10 +844,10 @@ static void determine_cpu_model(void)
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// Unknown processor - make a guess at the family.
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switch (cpuid_info.version.family) {
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case 5:
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cpu_model = "586";
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cpu_model = "586-class CPU (unknown)";
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break;
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case 6:
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cpu_model = "686";
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cpu_model = "686-class CPU (unknown)";
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break;
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default:
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cpu_model = "Unidentified Processor";
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