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Fix various temperature-related issues on older Atom CPUs

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Also, remove the no_temperature var to keep only the enable_temperature flag
Older Atom still have the enable_temperature flag hard-coded to false until further tests are done
This commit is contained in:
Sam Demeulemeester 2023-05-18 16:03:48 +02:00
parent 0b251df68d
commit de4f4768fc
5 changed files with 35 additions and 32 deletions
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8
app/config.c
View File

@ -840,8 +840,6 @@ void config_init(void)
cpu_state[i] = CPU_STATE_ENABLED;
}
enable_temperature &= !no_temperature;
power_save = POWER_SAVE_HIGH;
const boot_params_t *boot_params = (boot_params_t *)boot_params_addr;
@ -877,9 +875,9 @@ void config_menu(bool initial)
if (!smp_enabled) set_foreground_colour(BOLD+BLACK);
prints(POP_R+7, POP_LI, "<F5> CPU selection");
if (!smp_enabled) set_foreground_colour(WHITE);
if (no_temperature) set_foreground_colour(BOLD+BLACK);
//if (no_temperature) set_foreground_colour(BOLD+BLACK);
printf(POP_R+8, POP_LI, "<F6> Temperature %s", enable_temperature ? "disable" : "enable ");
if (no_temperature) set_foreground_colour(WHITE);
//if (no_temperature) set_foreground_colour(WHITE);
printf(POP_R+9, POP_LI, "<F7> Boot trace %s", enable_trace ? "disable" : "enable ");
prints(POP_R+10, POP_LI, "<F10> Exit menu");
} else {
@ -918,10 +916,8 @@ void config_menu(bool initial)
break;
case '6':
if (initial) {
if (!no_temperature) {
enable_temperature = !enable_temperature;
}
}
break;
case '7':
if (initial) {

1
app/display.c
View File

@ -343,7 +343,6 @@ void display_temperature(void)
if (actual_cpu_temp == 0) {
if (max_cpu_temp == 0) {
enable_temperature = false;
no_temperature = true;
}
return;
}

17
system/cpuinfo.c
View File

@ -50,8 +50,6 @@ uint32_t l2_cache_speed = 0;
uint32_t l3_cache_speed = 0;
uint32_t ram_speed = 0;
bool no_temperature = false;
uint32_t clks_per_msec = 0;
//------------------------------------------------------------------------------
@ -350,7 +348,8 @@ static void determine_imc(void)
imc.family = IMC_NHM; // Core i3/i5 1st Gen 45 nm (Nehalem/Bloomfield)
break;
case 3:
no_temperature = true; // Atom Clover Trail
imc.family = IMC_CLT;
enable_temperature = false; // Atom Clover Trail
break;
case 4:
imc.family = IMC_HSW_ULT; // Core 4th Gen (Haswell-ULT)
@ -365,9 +364,13 @@ static void determine_imc(void)
case 0x6:
switch (cpuid_info.version.extendedModel) {
case 2:
imc.family = IMC_TNC; // Atom Tunnel Creek / Lincroft
enable_temperature = false;
break;
case 3:
imc.family = IMC_CDT; // Atom Cedar Trail
no_temperature = true;
enable_temperature = false;
break;
case 4:
imc.family = IMC_HSW; // Core 4th Gen (Haswell w/ GT3e)
@ -431,9 +434,11 @@ static void determine_imc(void)
switch (cpuid_info.version.extendedModel) {
case 0x1:
if (cpuid_info.version.stepping > 9) {
imc.family = 0x0008; // Atom PineView
imc.family = IMC_PNV; // Atom PineView
} else {
imc.family = IMC_SLT; // Atom Silverthorne / Diamondvile
}
no_temperature = true;
enable_temperature = false;
break;
case 0x2:
imc.family = IMC_WMR; // Core i7 1st Gen 32 nm (Westmere)

11
system/cpuinfo.h
View File

@ -50,7 +50,11 @@
#define IMC_ADL_N 0x3061 // Core 12th Gen (Alder Lake-N - Gracemont E-Cores only)
#define IMC_BYT 0x4010 // Atom Bay Trail
#define IMC_CDT 0x4020 // Atom Cedar Trail
#define IMC_SLT 0x4020 // Atom Silverthorne / Diamondville
#define IMC_PNV 0x4030 // Atom Pineview
#define IMC_CLT 0x4040 // Atom Clover Trail / Cloverview
#define IMC_CDT 0x4050 // Atom Cedar Trail / Cedarview
#define IMC_TNC 0x4060 // Atom Tunnel Creek / Lincroft
#define IMC_K8 0x8000 // Old K8
#define IMC_K10 0x8010 // K10 (Family 10h & 11h)
@ -105,11 +109,6 @@ extern uint32_t l3_cache_speed;
*/
extern uint32_t ram_speed;
/**
* A flag indicating that we can't read the core temperature on this CPU.
*/
extern bool no_temperature;
/**
* The TSC clock speed in kHz. Assumed to be the nominal CPU clock speed.
*/

28
system/temperature.c
View File

@ -1,23 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2020-2022 Martin Whitaker.
// Copyright (C) 2004-2023 Sam Demeulemeester.
//
// Derived from an extract of memtest86+ init.c:
//
// MemTest86+ V5 Specific code (GPL V2.0)
// By Samuel DEMEULEMEESTER, sdemeule@memtest.org
// http://www.canardpc.com - http://www.memtest.org
// ------------------------------------------------
// init.c - MemTest-86 Version 3.6
//
// Released under version 2 of the Gnu Public License.
// By Chris Brady
#include <stdint.h>
#include "config.h"
#include "cpuid.h"
#include "cpuinfo.h"
#include "hwquirks.h"
#include "memctrl.h"
#include "msr.h"
#include "pci.h"
@ -41,8 +32,17 @@ void get_specific_TjMax(void)
// table according to their CPUID, PCI Root DID/VID or PNS.
// Trying to read the MSR 0x1A2 on some of them trigger a reboot.
// Yonah C0 Step (Pentium/Core Duo T2000 & Celeron M 200/400)
if (cpuid_info.version.raw[0] == 0x6E8) {
// Yonah C0 Step (Pentium/Core Duo T2000 & Celeron M 200/400)
TjMax = 100;
} else if (imc.family == IMC_SLT || imc.family == IMC_CLT || imc.family == IMC_TNC) {
// Atom Silverthorne / Diamondvile
// Atom Clover Trail/Cloverview
// Atom Tunnel Creek / Lincroft
TjMax = 90;
} else if (imc.family == IMC_CDT || imc.family == IMC_PNV) {
// Atom Silverthorne / Diamondvile
// Atom Cedar Trail/Cedarview
TjMax = 100;
}
}
@ -51,6 +51,10 @@ void temperature_init(void)
{
uint32_t regl, regh;
if (!enable_temperature) {
return;
}
// Process temperature-related quirks
if (quirk.type & QUIRK_TYPE_TEMP) {
quirk.process();