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Fix APIC Timer detection fail on some modern mobile/embedded PCH

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On some modern ULV cores (eg: Gracemont), the 2 following I/O reads to check APIC Timer working status are fused in the frontend, leading to the same value being reported twice and the code falling back to the (unusually disabled on these platforms) PIT timer.

Whether this behavior is intentional or not is unknown.

As usleep/sleep is not available at this point, a dirty delay is added between the two reads.
This commit is contained in:
Sam Demeulemeester 2023-04-23 22:45:11 +02:00
parent bfbb167a72
commit fa4e903509
1 changed files with 3 additions and 1 deletions
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4
system/timers.c
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@ -18,7 +18,6 @@
#define PIT_TICKS_50mS 59659 // PIT clock is 1.193182MHz
#define APIC_TICKS_50mS 178977 // APIC clock is 3.579545MHz
#define BENCH_MIN_START_ADR 0x1000000 // 16MB
//------------------------------------------------------------------------------
// Private Functions
@ -39,6 +38,9 @@ static void correct_tsc(void)
counter = inl(acpi_config.pm_addr);
// Generate a dirty delay
for(volatile uint8_t i=0; i<100u; i++);
// Make sure counter is incrementing
if (inl(acpi_config.pm_addr) > counter) {