From fe06e5d6410d031952faaf3e37460ef1be541aa2 Mon Sep 17 00:00:00 2001
From: Sam Demeulemeester <38105886+x86fr@users.noreply.github.com>
Date: Sun, 12 Jul 2026 15:37:06 +0200
Subject: [PATCH] Fix EPYC Temperature reporting (again) (#633)

Check CUR_TEMP_TJ_SEL for EPYC CPUs
---
 system/hwquirks.c        | 6 ++----
 system/x86/temperature.c | 9 +++++----
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/system/hwquirks.c b/system/hwquirks.c
index fa13b35..c223a51 100644
--- a/system/hwquirks.c
+++ b/system/hwquirks.c
@@ -175,10 +175,8 @@ static const amd_tctl_offset_t amd_tctl_offset_table[] = {
     { 0x8, 0x0, -27.0f, "AMD Ryzen Threadripper 19" },  // Whitehaven (1900X/1920X/1950X)
     { 0x8, 0x0, -27.0f, "AMD Ryzen Threadripper 29" },  // Colfax (29x0X/29x0WX)
     { 0x8, 0x0, -27.0f, "AMD EPYC 7"                },  // Naples (Family 17h, Model 01h)
-    //{ 0xA, 0xA, -49.0f, "AMD EPYC 8"                },  // Siena (Maybe needed)
-    //{ 0xA, 0x1, -49.0f, "AMD EPYC 9"                },  // Genoa (Maybe needed)
-    { 0xB, 0x0, -49.0f, "AMD EPYC 9"                },  // Turin (Family 19h, Model 11h)
-    // Other EPYC parts report Tdie directly using the bit-19 (T_OFFSET_PRESENT) path.
+    // EPYC Milan/Genoa/Siena/Turin need no entry here: their -49 °C range shift
+    // is detected generically via CUR_TEMP_RANGE_SEL / CUR_TEMP_TJ_SEL in cpu_temp_init().
 };
 
 static void amd_zen_apply_tctl_offset(void)
diff --git a/system/x86/temperature.c b/system/x86/temperature.c
index d602518..19a1b2a 100644
--- a/system/x86/temperature.c
+++ b/system/x86/temperature.c
@@ -79,14 +79,15 @@ void cpu_temp_init(void)
         }
     }
 
-    // On Zen and newer, check once whether firmware reports the generic
-    // -49 °C Tctl bias via T_OFFSET_PRESENT (bit 19). The result is folded
-    // into cpu_temp_offset so per-SKU quirks set above can still apply.
+    // On Zen and newer, apply the -49 °C range shift when signalled by
+    // CUR_TEMP_RANGE_SEL (bit 19) or CUR_TEMP_TJ_SEL (bits 17:16) == 0b11
+    // (BIOS-written register, typical on server parts). Folded into
+    // cpu_temp_offset so per-SKU quirks set above still apply.
     if (cpuid_info.vendor_id.str[0] == 'A' && cpuid_info.version.family == 0xF
         && cpuid_info.version.extendedFamily >= 8) {
 
         regl = amd_smn_read(SMN_THM_TCON_CUR_TMP);
-        if ((regl >> 19) & 0x01) {
+        if (((regl >> 19) & 0x1) || ((regl >> 16) & 0x3) == 0x3) {
             cpu_temp_offset += -49.0f;
         }
     }