* Add CPUID detection for MTL & ARL CPUs
* Add support for ARL SMBus Controler
Add PCI Device polling on Bus 0x80 (instead of fixed 0x00)
Solve issue with DDR5 SPD Bank switching when SPD Write is disabled (using Proc Call)
* Add Live Freq/Timings IMC Polling for Intel MTL & ADL CPUs
* Correct K8 Rev G detection
Fix#361 (PR hijacking)
* Split SPD parsing and printing code from smbus.c to spd.c
Move all SPD parsing and printing code from smbus.{c,h} to spd.{c,h}.
Introduce parse_spd() function, moving the parse_spd_* selection logic
from print_smbus_startup_info(), allowing to keep parse_spd_* static.
Remove static from get_spd() and update print_smbus_startup_info()
to use parse_spd() which also simplifies the code flow.
Move LINE_SPD into display.h and rename it to ROW_SPD. Update print_spdi()
to use explicit row number where the SPD info needs to be printed.
Rename ram_info into ram_info_t, rename print_smbus_startup_info()
into print_spd_startup_info.
Do not initialize ram.freq to 0, this is the initial value already.
Do not set curspd.isValid to False, the first thing that parse_spd()
does is setting the entire struct to 0, that also sets isValid to False.
print_spd_startup_info() from smbus.c is technically a skeleton now
so each arch can have its own version, adjusted as needed. Once
LA64 changes land, we can think how we can even make it arch agnostic.
* Add -fexcess-precision=standard to CFLAGS for build(32,64)/Makefile
Recent switch from -std=c11 to -std=gnu11 done in 53ca89f ("Add
initial NUMA awareness support") introduced a regression in SPD
parsing code (and potentially in other places) due to change of
floating point precision. Restore the original behavior by
adding -fexcess-precision=standard to CFLAGS.
Bug: https://github.com/memtest86plus/memtest86plus/issues/425
Fixes: 53ca89f8ae
Replace SPD SKU reading code repeated multiple times across
all the parse_spd_* functions with a dedicated read_sku function.
Convert spd_infos.sku from len+data into classic NULL-terminated C-string.
Takes the same space, but simplifies handling. Also, use char instead of
uint8_t so no conversion is needed when printing.
Change the way how the end of part number is handled. Stop on the first
non-ASCII character and then trim all trailing spaces. This allows SKUs
with two (or more) spaces inside the name to be handled properly.
Finally, fix incorrect / inconsistent part number length handling, with
the following end result:
- parse_spd_sdram: 18 [73-90] (no change)
- parse_spd_rdram: 18 [73-90] (no change)
- parse_spd_ddr: 18 [73-90] (no change)
- parse_spd_ddr2: 18 [73-90] (no change)
- parse_spd_ddr3: 20+1=21 -> 18 [128-145]
- parse_spd_ddr4: 20+1=21 -> 20 [329-348]
- parse_spd_ddr5: 29+1=30 -> 30 [521-550] (technicaly no change)
Before:
text data bss total filename
13143 3795 18 16956 build32/system/smbus.o
11735 4359 18 16112 build64/system/smbus.o
81705 51133 13088 145926 build32/memtest_shared
79686 58109 294432 432227 build64/memtest_shared
After:
text data bss total filename
10784 3887 18 14689 build32/system/smbus.o
10486 4399 18 14903 build64/system/smbus.o
79353 51101 13088 143542 build32/memtest_shared
78438 58077 294432 430947 build64/memtest_shared
gcc-11.3.0.
* [DDR5] Fix rounding errors on SPD Timings
* [DDR5] Add a rounding factor of ~0.3% according to JEDEC to solve the last rounding issue found on NETAC Modules
* [DDR5] Add missing package ranks per channel parameter in total module capacity algorithm
* [DDR4] Fix rounding issues in SPD timings & frequency
* [DDR3] Fix rounding issues in SPD timings & frequency decoding. Check XMP Profile #2. Add a quirk for Kingston based on very early XMP 1.0 specs
* [DDR2] Fix CAS detection & rounding issues in SPD timings w/ EPP
* [DDR] Correct SPD timings rounding issues & add support for x.5 CAS latencies
* [SDR] Correct SPD Timings decoding due to rounding errors
* Add various JEP106 Manufacturers found while debugging
* Update timings display function to handle x.5 CAS
Add a bunch of PCI device IDs and driver indications for other SMBus controllers, so as to avoid other persons having to do that work again.
Add support for two PIIX4 devices: the standard PIIX4 PCI device ID, and the ServerWorks CSB5, which has a slight twist.
Co-authored-by: Lionel Debroux <lionel_debroux@yahoo.fr>
Co-authored-by: Sam Demeulemeester <sam@x86.fr>
