* badram: Make DEFAULT_MASK depend on ARCH_BITS, not x86_64 architecture.
* badram: Don't display leading zeros for BadRAM addresses.
* badram: Merge patterns immediately when there is no additional cost.
The current algorithm only starts merging patterns when num_patterns
equals MAX_PATTERNS, which can lead to having several patterns that
could have been merged into one at no additional cost. e.g.
patterns = [
(0x00, 0xfffffffffffffff8),
(0x08, 0xfffffffffffffff8)
]
can appear, even though
patterns = [
(0x00, 0xfffffffffffffff0)
]
represents the exact same addresses at the same cost.
So, at the same time as we test whether an address is already covered,
also check if we can cheaply combine the new address with an existing
pattern.
* badram: Factor out code that wraps to a new line when necessary.
In preparation for next commit.
* badram: Add more modes for recording/displaying error maps.
The original code just supported recording and displaying patterns suitable
for use with the Linux BadRAM extension or GRUB badram command. With some
minor changes it can be made to record address ranges and display them
either in the format used by the Linux memmap boot command line option
or as a simple list of memory page numbers (which can be used with the
Windows bcdedit program).
* badram: Increase the number of stored patterns/ranges.
* Update README to include the new error reporting modes.
The x86_64 SysV calling convention does not require r8-r11 to be
preserved by the callee. So we need to save and restore them in the
low-level interrupt handling code in case the C interrupt() function
uses them.
* lib/assert: Add LoongArch assert support
Added LoongArch break 3 assert instruction.
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/barrier: Add barrier method for LoongArch
Added LoongArch barriers in barrier_spin_wait and barrier_halt_wait
functions.
Signed-off-by: Chao Li <lichao@loognson.cn>
* lib/spinlock: Add LoongArch CPU pause
Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/string: Make LoongArch use the string function in the file
Since LoongArch GCC doesn't have built-in string functions, use the
string function instance in the sting.c
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/unistd: Add LoongArch CPU pause
Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/acpi: Reduce the way of search RSDP for non-x86 ARCHs
Searching RSDP from legacy BIOS EDBA and reserved areas is available
only on i386 and x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/cache: Add LoongArch64 cache operations support
Added cache operations support for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/cpuid: Add the compile limit
Make the `cpuid` function action only on i386/x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/heap: Add heap support for LoongArch64
LoongArch64 uses the low 256MB as the low memory.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/memrw: Add 8-bit and 16-bit memory operations
Added 8-bit and 16-bit memory access operations, which 8-bit uses
`movb` and 16-bit is `movw`.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/memrw: Add LoongArch memory access operations
Added 8/16/32/64-bit memory access operations for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add Loongson PCI vendor ID and Loongson 7A chipset EHCI workaround
1. Added Loongson PCI vendor ID.
2. Added Loongson 7A chipset ECHI workaround.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/io: Add LoongArch64 IO port operations
Added IO port operations for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/reloc64: Add LoongArch64 relocations support
Added R_LARCH_RELATIVE and R_LARCH_NONE relocations support for
LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/serial: Add Loongson CPU serial port support
Add the serial port address perfix of Loongson CPU and obtain serial
port clock method.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/smbus: Rename smbus.c to i2c_x86.c
Renamed the smbus.c to i2c_x86.c in i386 and x64 platforms.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/smp: Add LoongArch SMP support
Added LoongArch multi-core support and a way of map to node numbers if
the NUMA is enabled.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/timers: Add LoongArch supports
In LoongArch, there is a stable counter that is independent of other
clocks, it like the TSC in x64. Using it to count the ticks per
millisecond.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/tsc: Add LoongArch support
Usually the frequency of stable counter is not same to CPU frequency, so
using the performance counter for the delay operations.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/usbhcd: Add LoongArch MMIO perfix
Added LoongArch64 MMIO address perfix, use for address the PCI memory
space.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/usbhcd: Add Loongson 7A2000 chipset OHCI BAR offset fix
If the BAR address is not fixed for the Loongson 7A2000 OHCI controller,
some prots will not be usable, This change currently only affects the
LoongArch platform.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add the way to IO access via MMIO
Usually, it is access the IO like PCI IO via MMIO on non-X86 ARCHs, so
a method to access IO via MMIO is added.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add the way to access PCI memory space via MMIO
Some uniformly address ARCHs access the PCI memory depended the MMIO, so
the method to access PCI memory via MMIO is added.
Signed-off-by: Chao Li <lichao@loongson.cn>
* app: Add LoongArch version support
Reduced the version field by two characters to support ARCH name
abbreviations with more than three characters, and added "la64" ARCH
version display.
Singed-off-by: Chao Li <lichao@loongson.cn>
* test/block_move: Add block move test via ASM for LoongArch
Add block move test inline assembly instance for LoongArch.
Signed-off-by: Chao Li <lichao@loongson.cn>
* test/mov_inv_fixed: Add LoongArch ASM version word write operation
Add LoongArch ASM version word write cycle if it uses the HAND_OPTIMISED.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot: Adjust the AP stack size for LoongArch
LoongArch exception will store all of the GP, FP and CSR on stack, it
need more stack size, make LoongArch AP using 2KB stack size.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot/efisetup: Add LoongArch CPU halt instruction
Add "idle 0" for LoongArch
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot/efi: Limiting the ms_abi using scope
Make the ms_abi only work on i386 and x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/imc/loongson: Add Loongson LoongArch IMC support
Added the Loongson LoongArch CPU IMC instance, support read out the IMC
sequence, currently only supports reading MC0.
Signed-off-by: Chao Li <lichao@loongson.cn>
* app/loongarch: Add intrrupt handler for LoongArch
Added the LoongArch IRQ handler support.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/loongarch: Add LoongArch ARCH specific files
Added LoongArch ARCH specific files: cpuid.c, cpuinfo.c, hwctrl.c,
memctrl.c, temperature.c, vmem.c, registers.h
They use the same pubilc API for i386 and x64 platforms.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot: Add LoongArch startup and header
Added the header.S and startup64.S for LoongArch, CPU works on:
1. Page mode.
2. Load and store is cacheable.
3. Instructions is cacheable.
4. DMWn 0 and 1 is used.
5. To access non-cacheable areas, use the perfix 0x8000000000000000.
Signed-off Chao Li <lichao@loongson.cn>
* build64/la64: Add LoongArch64 build files
Add infrastructure files to build memtest86 plus for LoongArch64
platform.
Signed-off-by: Chao Li <lichao@loongson.cn>
* workflows: Add LoongArch64 CI supports
Adjust workflow logci, remvoe 32 and 64 wordsize, replace with "i386,
x86_64 and la64", add LoongArch64 build CI check.
Signed-off-by: Chao Li <lichao@loongson.cn>
---------
Signed-off-by: Chao Li <lichao@loongson.cn>
Signed-off-by: Chao Li <lichao@loognson.cn>
* Split SPD parsing and printing code from smbus.c to spd.c
Move all SPD parsing and printing code from smbus.{c,h} to spd.{c,h}.
Introduce parse_spd() function, moving the parse_spd_* selection logic
from print_smbus_startup_info(), allowing to keep parse_spd_* static.
Remove static from get_spd() and update print_smbus_startup_info()
to use parse_spd() which also simplifies the code flow.
Move LINE_SPD into display.h and rename it to ROW_SPD. Update print_spdi()
to use explicit row number where the SPD info needs to be printed.
Rename ram_info into ram_info_t, rename print_smbus_startup_info()
into print_spd_startup_info.
Do not initialize ram.freq to 0, this is the initial value already.
Do not set curspd.isValid to False, the first thing that parse_spd()
does is setting the entire struct to 0, that also sets isValid to False.
print_spd_startup_info() from smbus.c is technically a skeleton now
so each arch can have its own version, adjusted as needed. Once
LA64 changes land, we can think how we can even make it arch agnostic.
* Add -fexcess-precision=standard to CFLAGS for build(32,64)/Makefile
Recent switch from -std=c11 to -std=gnu11 done in 53ca89f ("Add
initial NUMA awareness support") introduced a regression in SPD
parsing code (and potentially in other places) due to change of
floating point precision. Restore the original behavior by
adding -fexcess-precision=standard to CFLAGS.
Bug: https://github.com/memtest86plus/memtest86plus/issues/425
Fixes: 53ca89f8ae
Added a new CC flag into build32 and build64 Makefiles to distinguish
whether compiling to 32-bit or 64-bit code.
[Lionel Debroux: rebased on the memrw functions refactor.]
Signed-off-by: Chao Li <lichao@loongson.cn>
* Add a file containing useful macro definitions, currently a single top-level macro for obtaining the size of an array; use it to replace a sizeof(x) / sizeof(x[0]) construct in system/smbus.c . This requires switching the GCC build mode from C11 to C11 with GCC extensions.
* Initial NUMA awareness (#12) support: parse the ACPI SRAT to build up new internal structures related to proximity domains and affinity; use these structures in setup_vm_map() and calculate_chunk() to skip the work on the processors which don't belong to the proximity domain currently being tested.
Tested on a number of 1S single-domain, 2S multi-domain and 4S multi-domain platforms.
SKIP_RANGE(iterations) trick by Martin Whitaker.
This was mentioned in the individual test descriptions in the README,
but easily missed (issue #384). Add a note in the BadRAM section of
the README and also in the error display heading.
* Initial commit for ECC support. Preliminary support for AMD Zen.
* Clear ECC registers at startup
* Add config flag (enable_ecc_polling) to toggle ECC polling. (Currently disabled by default for v7 release)
* Optimize the JEP106 list by using __attribute__((packed)) to remove padding. The x86 & x86_64 series support unaligned accesses just fine, after all, and this is not remotely a hot path.
* Optimize several string-related constructs by switching to fixed-length char arrays, which avoids pointers + relocations.
* app/interrupt.c: array of different-length strings, but most of those are lengthy enough for this to be a clear win, especially on x86_64;
* system/usbhcd.c: array of same-length strings;
* tests/tests.h: array of structs containing same-length strings.
* Reduce the size of the list of tests by using a narrower type for the cpu mode, which reduces padding.
Also, remove the no_temperature var to keep only the enable_temperature flag
Older Atom still have the enable_temperature flag hard-coded to false until further tests are done
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings.
Currently supported platforms:
* Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile)
* AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU).
Individual commits below for archival:
* First functions skeleton for reading IMC/ECC Registers
* Change directory name from 'chipsets' to 'mch' (Memory Controller Hub)
* Add Intel HSW and fix new files encoding
* First Intel HSW IMC implementation
* Add an option to disable MCH registers polling
* Remove old include from Makefiles
* Better Makefile and padding fixes
* Statically init 'imc' struct to generate string relocation record
* Small typos & code fixes
* Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed
* Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core)
* Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer
* Move AMD SMN Registers & offsets to a specific header file
* Add IMC Read support for AMD Zen/Zen2 CPUs
* Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory
* Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13)
* Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer
* Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs
* Various Cleanup #1
Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file
* Various Cleanup 2
* Change DDR5 display format for IMC specs
DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space.
This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
* BadRAM: Rename pattern -> patterns
* BadRAM: Refactor COMBINE_MASK and add clarifying comment
* BadRAM: Extract DEFAULT_MASK into variable
* BadRAM: Add is_covered() for checking if pattern is already covered by one of the existing patterns
* BadRAM: Initialize patterns to 0
* BadRAM: Change how addr/masks are merged to minimize number of addresses covered by badram
Prior to this patch, a list of up to MAX_PATTERNS (=10) addr/mask tuples
(aka. pattern) were maintained, adding failing addresses one by one to
the list until it was full. When full, space was created by forcing a
merge of the new address with the existing pattern that would grow the
least (with regards to number of addresses covered by the pattern) by
merging it with the new address. This can lead to a great imbalance in
the number of addresses covered by the patterns. Consider the following:
MAX_PATTERNS=4 (for illustrative purposes).
The following addresses are faulted and added to patterns:
0x00, 0x10, 0x20, 0x68, 0xa0, 0xb0, 0xc0, 0xd0
This is the end result with the implementation prior to this commit:
patterns = [
(0x00, 0xe8),
(0x00, 0x18),
(0x68, 0xf8),
(0x90, 0x98)
]
Total addresses covered: 120.
This commit changes how the merges are done, not only considering a
merge between the new address and existing patterns, but also between
existing patterns. It keeps the patterns in ascending order (by .addr)
in patterns, and a new address is always inserted into patterns (even if
num_patterns == MAX_PATTERNS, patterns is of MAX_PATTERNS+1 size). Then,
if num_patterns > MAX_PATTERNS, we find the pair of patterns (only
considering neighbours, assuming for any pattern i, i-1 or i+1 will
be the best candidate for a merge) that would be the cheapest to
merge (using the same metric as prior to this patch), and merge those.
With this commit, this is the result of the exact same sequence of
addresses as above:
[
(0x00, 0xe0),
(0x68, 0xf8),
(0xa0, 0xe8),
(0xc0, 0xe8)
]
Total addresses covered: 72.
A drawback of the current implementation (as compared to the prior)
is that it does not make any attempt at merging patterns until
num_patterns == MAX_PATTERNS, which can lead to having several patterns
that could've been merged into one at no additional cost. I.e.:
patterns = [
(0x00, 0xf8),
(0x08, 0xf8)
]
can appear, even if
patterns = [
(0x00, 0xf0)
]
represents the exact same addresses with one pattern instead of two.
* fixup! BadRAM: Change how addr/masks are merged to minimize number of addresses covered by badram
Co-authored-by: Anders Wenhaug <anders.wenhaug@solutionseeker.no>
smp_init() used to be called after the startup dialogue, so F2 only
needed to change the enable_smp flag. Now smp_init() is called earlier,
we also need to reset num_available_cpus.
By default, don't re-display FAIL banner after it has been discarded (#130 & #173)
Add an option to re-display FAIL banner even if previously discarded
* Avoid FAIL banner being partially overwriten by new errors
* Remove beta on main title
* Remove v6 Beta Disclaimer & some README.me changes for release
* [DDR5] Fix rounding errors on SPD Timings
* [DDR5] Add a rounding factor of ~0.3% according to JEDEC to solve the last rounding issue found on NETAC Modules
* [DDR5] Add missing package ranks per channel parameter in total module capacity algorithm
* [DDR4] Fix rounding issues in SPD timings & frequency
* [DDR3] Fix rounding issues in SPD timings & frequency decoding. Check XMP Profile #2. Add a quirk for Kingston based on very early XMP 1.0 specs
* [DDR2] Fix CAS detection & rounding issues in SPD timings w/ EPP
* [DDR] Correct SPD timings rounding issues & add support for x.5 CAS latencies
* [SDR] Correct SPD Timings decoding due to rounding errors
* Add various JEP106 Manufacturers found while debugging
* Update timings display function to handle x.5 CAS
Most legacy BIOSs will support USB legacy keyboard emulation. Using that
will avoid having to reserve memory for the USB drivers, and should
improve the chance of having a working keyboard without having to work
around various USB device quirks.
* Add new heap manager.
* Convert OHCI driver to use new heap manager.
* Convert UHCI driver to use new heap manager.
* Convert EHCI driver to use new heap manager.
* Convert XHCI driver to use new heap manager.
* Convert SMP to use new heap manager.
* Add a "usbinit" boot option to handle various buggy USB devices.
This replaces the "keyboard=buggy-usb" option, and adds a second
workaround to handle the problem seen in issue #107.
Add AP Enumeration to distinguish E-Core from P-Core on Intel Hybrid CPUs, and exclude them from the selected cores by default. Including E-Cores slows down some tests and takes longer to catch memory errors.
A new exclude_ecores flag has been added in config.c to include E-Cores if needed.
- Enable VGA/FB to output box drawing characters while maintaining VT100
character set for serial. Shorten and simplify the screen setup code.
- Track the background color to decide if the serial output needs to be
inverted. Remove no longer needed logic for known areas of the screen that
need to be inverted. As a bonus - popup menu can now be also inverted on
serial.
- Reduce the amount of data sent to serial by using CR+LF when possible
instead of always relying on absolute positioning. Add tty_print()
for positioning the cursor, remove no longer needed tty_print().
- Remove no longer needed "LF -> LF+CR" logic from serial_echo_print().
Before (gcc-11.3.0-x86_64):
text data bss total filename
929 357 64 1350 system/serial.o
3517 1356 54 4927 app/display.o
After (gcc-11.3.0-x86_64):
text data bss total filename
907 336 64 1307 system/serial.o
3442 1242 54 4738 app/display.o
Co-authored-by: Sam Demeulemeester <38105886+x86fr@users.noreply.github.com>
