* lib/assert: Add LoongArch assert support
Added LoongArch break 3 assert instruction.
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/barrier: Add barrier method for LoongArch
Added LoongArch barriers in barrier_spin_wait and barrier_halt_wait
functions.
Signed-off-by: Chao Li <lichao@loognson.cn>
* lib/spinlock: Add LoongArch CPU pause
Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/string: Make LoongArch use the string function in the file
Since LoongArch GCC doesn't have built-in string functions, use the
string function instance in the sting.c
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/unistd: Add LoongArch CPU pause
Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/acpi: Reduce the way of search RSDP for non-x86 ARCHs
Searching RSDP from legacy BIOS EDBA and reserved areas is available
only on i386 and x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/cache: Add LoongArch64 cache operations support
Added cache operations support for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/cpuid: Add the compile limit
Make the `cpuid` function action only on i386/x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/heap: Add heap support for LoongArch64
LoongArch64 uses the low 256MB as the low memory.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/memrw: Add 8-bit and 16-bit memory operations
Added 8-bit and 16-bit memory access operations, which 8-bit uses
`movb` and 16-bit is `movw`.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/memrw: Add LoongArch memory access operations
Added 8/16/32/64-bit memory access operations for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add Loongson PCI vendor ID and Loongson 7A chipset EHCI workaround
1. Added Loongson PCI vendor ID.
2. Added Loongson 7A chipset ECHI workaround.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/io: Add LoongArch64 IO port operations
Added IO port operations for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/reloc64: Add LoongArch64 relocations support
Added R_LARCH_RELATIVE and R_LARCH_NONE relocations support for
LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/serial: Add Loongson CPU serial port support
Add the serial port address perfix of Loongson CPU and obtain serial
port clock method.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/smbus: Rename smbus.c to i2c_x86.c
Renamed the smbus.c to i2c_x86.c in i386 and x64 platforms.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/smp: Add LoongArch SMP support
Added LoongArch multi-core support and a way of map to node numbers if
the NUMA is enabled.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/timers: Add LoongArch supports
In LoongArch, there is a stable counter that is independent of other
clocks, it like the TSC in x64. Using it to count the ticks per
millisecond.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/tsc: Add LoongArch support
Usually the frequency of stable counter is not same to CPU frequency, so
using the performance counter for the delay operations.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/usbhcd: Add LoongArch MMIO perfix
Added LoongArch64 MMIO address perfix, use for address the PCI memory
space.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/usbhcd: Add Loongson 7A2000 chipset OHCI BAR offset fix
If the BAR address is not fixed for the Loongson 7A2000 OHCI controller,
some prots will not be usable, This change currently only affects the
LoongArch platform.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add the way to IO access via MMIO
Usually, it is access the IO like PCI IO via MMIO on non-X86 ARCHs, so
a method to access IO via MMIO is added.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add the way to access PCI memory space via MMIO
Some uniformly address ARCHs access the PCI memory depended the MMIO, so
the method to access PCI memory via MMIO is added.
Signed-off-by: Chao Li <lichao@loongson.cn>
* app: Add LoongArch version support
Reduced the version field by two characters to support ARCH name
abbreviations with more than three characters, and added "la64" ARCH
version display.
Singed-off-by: Chao Li <lichao@loongson.cn>
* test/block_move: Add block move test via ASM for LoongArch
Add block move test inline assembly instance for LoongArch.
Signed-off-by: Chao Li <lichao@loongson.cn>
* test/mov_inv_fixed: Add LoongArch ASM version word write operation
Add LoongArch ASM version word write cycle if it uses the HAND_OPTIMISED.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot: Adjust the AP stack size for LoongArch
LoongArch exception will store all of the GP, FP and CSR on stack, it
need more stack size, make LoongArch AP using 2KB stack size.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot/efisetup: Add LoongArch CPU halt instruction
Add "idle 0" for LoongArch
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot/efi: Limiting the ms_abi using scope
Make the ms_abi only work on i386 and x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/imc/loongson: Add Loongson LoongArch IMC support
Added the Loongson LoongArch CPU IMC instance, support read out the IMC
sequence, currently only supports reading MC0.
Signed-off-by: Chao Li <lichao@loongson.cn>
* app/loongarch: Add intrrupt handler for LoongArch
Added the LoongArch IRQ handler support.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/loongarch: Add LoongArch ARCH specific files
Added LoongArch ARCH specific files: cpuid.c, cpuinfo.c, hwctrl.c,
memctrl.c, temperature.c, vmem.c, registers.h
They use the same pubilc API for i386 and x64 platforms.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot: Add LoongArch startup and header
Added the header.S and startup64.S for LoongArch, CPU works on:
1. Page mode.
2. Load and store is cacheable.
3. Instructions is cacheable.
4. DMWn 0 and 1 is used.
5. To access non-cacheable areas, use the perfix 0x8000000000000000.
Signed-off Chao Li <lichao@loongson.cn>
* build64/la64: Add LoongArch64 build files
Add infrastructure files to build memtest86 plus for LoongArch64
platform.
Signed-off-by: Chao Li <lichao@loongson.cn>
* workflows: Add LoongArch64 CI supports
Adjust workflow logci, remvoe 32 and 64 wordsize, replace with "i386,
x86_64 and la64", add LoongArch64 build CI check.
Signed-off-by: Chao Li <lichao@loongson.cn>
---------
Signed-off-by: Chao Li <lichao@loongson.cn>
Signed-off-by: Chao Li <lichao@loognson.cn>
* Split SPD parsing and printing code from smbus.c to spd.c
Move all SPD parsing and printing code from smbus.{c,h} to spd.{c,h}.
Introduce parse_spd() function, moving the parse_spd_* selection logic
from print_smbus_startup_info(), allowing to keep parse_spd_* static.
Remove static from get_spd() and update print_smbus_startup_info()
to use parse_spd() which also simplifies the code flow.
Move LINE_SPD into display.h and rename it to ROW_SPD. Update print_spdi()
to use explicit row number where the SPD info needs to be printed.
Rename ram_info into ram_info_t, rename print_smbus_startup_info()
into print_spd_startup_info.
Do not initialize ram.freq to 0, this is the initial value already.
Do not set curspd.isValid to False, the first thing that parse_spd()
does is setting the entire struct to 0, that also sets isValid to False.
print_spd_startup_info() from smbus.c is technically a skeleton now
so each arch can have its own version, adjusted as needed. Once
LA64 changes land, we can think how we can even make it arch agnostic.
* Add -fexcess-precision=standard to CFLAGS for build(32,64)/Makefile
Recent switch from -std=c11 to -std=gnu11 done in 53ca89f ("Add
initial NUMA awareness support") introduced a regression in SPD
parsing code (and potentially in other places) due to change of
floating point precision. Restore the original behavior by
adding -fexcess-precision=standard to CFLAGS.
Bug: https://github.com/memtest86plus/memtest86plus/issues/425
Fixes: 53ca89f8ae
Added a new CC flag into build32 and build64 Makefiles to distinguish
whether compiling to 32-bit or 64-bit code.
[Lionel Debroux: rebased on the memrw functions refactor.]
Signed-off-by: Chao Li <lichao@loongson.cn>
People creating the media through File System Transposition [1] rather than DD
copy may end up with a media that uses a GPT partition table rather than MBR.
So add GPT support to GRUB, as a low cost beneficial change.
For reference, File System Transposition is the default method used by Rufus
and other utilities for creating bootable media from an ISO, and it allows
users to select GPT instead over MBR, in which case memtest86+ will not boot.
[1] https://lists.gnu.org/archive/html/grub-devel/2022-06/msg00024.html
* Add a file containing useful macro definitions, currently a single top-level macro for obtaining the size of an array; use it to replace a sizeof(x) / sizeof(x[0]) construct in system/smbus.c . This requires switching the GCC build mode from C11 to C11 with GCC extensions.
* Initial NUMA awareness (#12) support: parse the ACPI SRAT to build up new internal structures related to proximity domains and affinity; use these structures in setup_vm_map() and calculate_chunk() to skip the work on the processors which don't belong to the proximity domain currently being tested.
Tested on a number of 1S single-domain, 2S multi-domain and 4S multi-domain platforms.
SKIP_RANGE(iterations) trick by Martin Whitaker.
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings.
Currently supported platforms:
* Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile)
* AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU).
Individual commits below for archival:
* First functions skeleton for reading IMC/ECC Registers
* Change directory name from 'chipsets' to 'mch' (Memory Controller Hub)
* Add Intel HSW and fix new files encoding
* First Intel HSW IMC implementation
* Add an option to disable MCH registers polling
* Remove old include from Makefiles
* Better Makefile and padding fixes
* Statically init 'imc' struct to generate string relocation record
* Small typos & code fixes
* Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed
* Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core)
* Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer
* Move AMD SMN Registers & offsets to a specific header file
* Add IMC Read support for AMD Zen/Zen2 CPUs
* Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory
* Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13)
* Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer
* Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs
* Various Cleanup #1
Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file
* Various Cleanup 2
* Change DDR5 display format for IMC specs
DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space.
This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
We have a .setup section in the EFI image that contains the remainder of
the Linux boot header and the real-mode setup code to support booting via
an intermediate bootloader. This sits between the PE header and the .text
section. We don't want the EFI loader to load this section, so simply
increase the SizeOfHeader field in the PE header to cover it.
When the reloc and sbat sections were added by PR #34, three bugs were
introduced:
1. The virtual address and size fields in the PE headers were set to the
same values as the raw address and size fields. This is incorrect, because
the sections in the image file are aligned on 512 byte boundaries, but when
loaded into memory they need to be aligned on 4096 byte boundaries.
2. The value programmed into the SizeOfImage field was too large, as it
double-counted the region before the start of the .text section.
3. The value programmed into the SizeOfImage field no longer included the bss
size. That potentially allowed the EFI loader to load the image immediately
before a reserved region of memory without leaving enough space for the bss
section.
This commit fixes those bugs by calculating both file and virtual memory
offsets & sizes in the ld script. Note that we can't add a bss section to the
EFI image because many EFI loaders fail to load images that have uninitialised
data sections. Instead the text region size in virtual memory is increased
to include the bss size.
This fixes issue #243. It also eliminates the gaps between sections
observed in issue #202.
This patch adds a new section, ".sbat", which allows for the revocation
of signed binaries given a numeric value representing the set of bugs
which allow for arbitrary code execution, and therefore a Secure Boot
breakout, in a given family of binaries.
In this case, the class is defined as "memtest86+", and the current set
of bugs is 1. This doesn't imply that we're aware of bugs currently,
merely that when we change it to 2, any bugs that /have/ been discovered
have been fixed.
Documentation for how SBAT works can be found at the following URLs:
https://github.com/rhboot/shim/blob/main/SBAT.mdhttps://github.com/rhboot/shim/blob/main/SBAT.example.md
Signed-off-by: Peter Jones <pjones@redhat.com>
In the past, we've seen some problems with some EFI loaders refusing to
load a binary that has both a .text section with the VMA set and no
relocations, when the VMA set to load is already allocated for some
other purpose.
This patch adds a dummy absolute relocation from 0 to 0, so the loader
can always feel like it has done something useful.
Signed-off-by: Peter Jones <pjones@redhat.com>
SizeOfImage is defined as:
The size (in bytes) of the image, including all headers, as the image
is loaded in memory. It must be a multiple of SectionAlignment.
SizeOfHeaders likewise is defined as:
The combined size of an MS-DOS stub, PE header, and section headers
rounded up to a multiple of FileAlignment.
Currently SizeOfImage represents .bss and .text, but it doesn't include
.header or .setup, nor any sections we'll add later, and there's nothing
enforcing that it matches SectionAlignment. Additionally, since .bss is
being set up in our running code and /not/ by the loader, the current
value is dangerously high, as in the event there is an error in the
section table, it could potentially lead the loader to mark memory
allocated at runtime holding user-supplied data by any EFI binary loaded
before us as executable.
This patch adds a new symbol, _img_end, which is after .text and is
rounded up to 4kB (which is also what SectionAlignment is set to). It
also adds a local label, anchored with ".org 512", and uses that to set
SizeOfHeaders - this will ensure the build fails without outputting and
invalid binary if the headers take too much space.
Signed-off-by: Peter Jones <pjones@redhat.com>
This patch makes it so we use "gcc -x assembler-with-cpp" to build our
.S files, instead of translating them to .s files and assembling
directly. This allows us to use header files and simple symbolic
arithmetic more conveniently in .S files, and at the same time reduces
the number of temporary files created when building.
Signed-off-by: Peter Jones <pjones@redhat.com>
grub-memtest.iso was originally intended as a means of testing all
the different boot modes. But as we publish it on memtest.org, let's
have a more user-friendly version that provides menu entries for the
most commonly needed boot options. The original test ISO can still
be built by 'make GRUB_CFG=grub-test grub-iso'.
* Add new heap manager.
* Convert OHCI driver to use new heap manager.
* Convert UHCI driver to use new heap manager.
* Convert EHCI driver to use new heap manager.
* Convert XHCI driver to use new heap manager.
* Convert SMP to use new heap manager.
* Add a "usbinit" boot option to handle various buggy USB devices.
This replaces the "keyboard=buggy-usb" option, and adds a second
workaround to handle the problem seen in issue #107.
* Add preliminary support for TTY Serial/UART (#15)
* Use shadow_buffer instead of VGA buffer to get a framebuffer-agnostic TTY supprot
* Added menu browsing & inputs from Serial TTY (#15)
* Add fix for degree symbol on TTY. Correct serial.c & serial.h file created with CRLF (#15)
* Move tty_error_redraw() to insure correct redraw when a error occurs
* Many reindent / cleanup
* Various optimization from @martinwhitaker comments
The old barrier implementation was very slow when running on a multi-socket
machine (pcmemtest issue 16).
The new implementation provides two options:
- when blocked, spin on a thread-local flag
- when blocked, execute a HLT instruction and wait for a NMI
The first option might be faster, but we need to measure it to find out. A
new boot command line option is provided to select between the two, with a
third setting that uses a mixture of the two.
When using a legacy BIOS, the memory regions used by the BIOS are well
defined. This is not the case when using a UEFI BIOS. So include the
stack area in the BSS so the loader knows how much memory to allocate,
and check we have space to relocate the program to either low or high
memory.
There are still some assumptions in the USB driver code that need to
be fixed.
