* cpuinfo: Add support for Vortex86
Hardcode cache for family 5, use CPUID cache info for family 6.
* cpuinfo: Add support for Vortex86EX
The EX does not have brand string so hardcode name and cache.
* In determine_cache_size(), add an additional test to ensure that only
Vortex86 CPUs are handled, allowing Zhaoxin CPUs to fall through.
Also, remove the no_temperature var to keep only the enable_temperature flag
Older Atom still have the enable_temperature flag hard-coded to false until further tests are done
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings.
Currently supported platforms:
* Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile)
* AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU).
Individual commits below for archival:
* First functions skeleton for reading IMC/ECC Registers
* Change directory name from 'chipsets' to 'mch' (Memory Controller Hub)
* Add Intel HSW and fix new files encoding
* First Intel HSW IMC implementation
* Add an option to disable MCH registers polling
* Remove old include from Makefiles
* Better Makefile and padding fixes
* Statically init 'imc' struct to generate string relocation record
* Small typos & code fixes
* Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed
* Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core)
* Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer
* Move AMD SMN Registers & offsets to a specific header file
* Add IMC Read support for AMD Zen/Zen2 CPUs
* Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory
* Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13)
* Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer
* Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs
* Various Cleanup #1
Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file
* Various Cleanup 2
* Change DDR5 display format for IMC specs
DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space.
This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
On some modern ULV cores (eg: Gracemont), the 2 following I/O reads to check APIC Timer working status are fused in the frontend, leading to the same value being reported twice and the code falling back to the (unusually disabled on these platforms) PIT timer.
Whether this behavior is intentional or not is unknown.
As usleep/sleep is not available at this point, a dirty delay is added between the two reads.
* cpuinfo: Fix WinChip and Cyrix/NSC CPU name and cache info
Always populate the cache info from extended CPUID, it is not used for
Intel CPUs, even though it is present, and is useful for non-Intel CPUs.
Fix the CPU name and cache sizes for Centaur and Cyrix/NSC CPUs without
brand string, which are the WinChip C6 and all Cyrix CPUs except the
Media GXm.
For the Media GXm and Geode GXm/GXLV/GX1, which are available with both
Cyrix and NSC vendor strings, hardcode the L1 cache size. The Geode GX2
uses standard cache info.
* Add 'Intel' in CPU names for older CPUs
* Add 'Transmeta' and 'IDT' in CPU names for older CPUs
-------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs
Use extended CPUID for VIA C3/C7/Nano cache information.
Use MSR reads for Nano/Zhaoxin and VIA C7 processor temperature.
Tested on VIA C7-D 1.5GHz.
* Small code conventions fixes
* Fix overallocation of cpuid_cache_info_t union (From PR #263)
---------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
A headless EFI system may have no GOP devices. In this case, disable
output to the physical display, but continue to write to the shadow
buffer. This allows operation via a serial console.
When two controllers are attached to a physical port (e.g. in the
case of EHCI and its companion controllers, problems can occur if
the BIOS still has control of one controller when we try to use the
other one. So perform a first pass to scan the PCI bus and take
ownership of and reset all the controllers we find, and perform a
second pass to initialise the controllers and probe for attached
devices.
As we don't support hot plugging, split the second pass into two,
with the first probing the EHCI controllers and handing over any
low and full speed devices to the companion controllers, and the
second probing the remaining controller types.
Introduce bcd_to_ui8 for converting BCD into uint8_t.
Currently, smbus.c is the only user of this code so I placed it there.
Once (if?) there are more, we may want to move it to a dedicated ".h" file.
Replace all BCD conversion in smbus.c with a call to bcd_to_ui8().
No change in the binary output.
Convert calling / return convention for all parse_spd_* functions from
returning the value of spd_info structure to updating the received
reference. This also allows to move / remove some boilerplate code,
like initializing spdi/curspd and setting slot_num.
At the end, print_smbus_startup_info wants curspd to be updated,
so we can do this in a more efficient way.
Before:
text data bss total filename
10784 3887 18 14689 build32/system/smbus.o
10486 4399 18 14903 build64/system/smbus.o
79353 51101 13088 143542 build32/memtest_shared
78438 58077 294432 430947 build64/memtest_shared
After:
text data bss total filename
10379 3871 18 14268 build32/system/smbus.o
9833 4399 18 14250 build64/system/smbus.o
78937 51101 13088 143126 build32/memtest_shared
77782 58077 294432 430291 build64/memtest_shared
gcc-11.3.0.
Replace SPD SKU reading code repeated multiple times across
all the parse_spd_* functions with a dedicated read_sku function.
Convert spd_infos.sku from len+data into classic NULL-terminated C-string.
Takes the same space, but simplifies handling. Also, use char instead of
uint8_t so no conversion is needed when printing.
Change the way how the end of part number is handled. Stop on the first
non-ASCII character and then trim all trailing spaces. This allows SKUs
with two (or more) spaces inside the name to be handled properly.
Finally, fix incorrect / inconsistent part number length handling, with
the following end result:
- parse_spd_sdram: 18 [73-90] (no change)
- parse_spd_rdram: 18 [73-90] (no change)
- parse_spd_ddr: 18 [73-90] (no change)
- parse_spd_ddr2: 18 [73-90] (no change)
- parse_spd_ddr3: 20+1=21 -> 18 [128-145]
- parse_spd_ddr4: 20+1=21 -> 20 [329-348]
- parse_spd_ddr5: 29+1=30 -> 30 [521-550] (technicaly no change)
Before:
text data bss total filename
13143 3795 18 16956 build32/system/smbus.o
11735 4359 18 16112 build64/system/smbus.o
81705 51133 13088 145926 build32/memtest_shared
79686 58109 294432 432227 build64/memtest_shared
After:
text data bss total filename
10784 3887 18 14689 build32/system/smbus.o
10486 4399 18 14903 build64/system/smbus.o
79353 51101 13088 143542 build32/memtest_shared
78438 58077 294432 430947 build64/memtest_shared
gcc-11.3.0.
* [DDR5] Fix rounding errors on SPD Timings
* [DDR5] Add a rounding factor of ~0.3% according to JEDEC to solve the last rounding issue found on NETAC Modules
* [DDR5] Add missing package ranks per channel parameter in total module capacity algorithm
* [DDR4] Fix rounding issues in SPD timings & frequency
* [DDR3] Fix rounding issues in SPD timings & frequency decoding. Check XMP Profile #2. Add a quirk for Kingston based on very early XMP 1.0 specs
* [DDR2] Fix CAS detection & rounding issues in SPD timings w/ EPP
* [DDR] Correct SPD timings rounding issues & add support for x.5 CAS latencies
* [SDR] Correct SPD Timings decoding due to rounding errors
* Add various JEP106 Manufacturers found while debugging
* Update timings display function to handle x.5 CAS
Some CPU like Intel Yorkfield (Core 2 Quad) reports max CPUID > 0xB but doesn't support CPUID = 0xB. Check x2apic flag to be sure CPUID 0xB is supported. If not, fallback to older detection method
Most legacy BIOSs will support USB legacy keyboard emulation. Using that
will avoid having to reserve memory for the USB drivers, and should
improve the chance of having a working keyboard without having to work
around various USB device quirks.
