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103 Commits

Author SHA1 Message Date
Sam Demeulemeester
eae5dd2796 Correct TTY to match the new temperature location on display 2022-04-16 13:31:28 +02:00
Sam Demeulemeester
6fca9bedc9 Rework Line 9. Add DDR1->DDR5 Timing Detection to display on this line 2022-04-16 13:31:28 +02:00
Sam Demeulemeester
979b85548d Rework Line #7 left block. Add preliminary CPUID function to detect CPU Topology 2022-04-16 13:31:28 +02:00
Martin Whitaker
2cd060b22c Fix warning about mismatched comparison operands in 32-bit build. 2022-04-13 14:20:46 +01:00
Martin Whitaker
9f92ecf761 Fix the remapping of the screen frame buffer. 
The size of the region to be mapped is determined by the buffer stride,
not the pixel width.
 2022-04-11 21:46:49 +01:00
Martin Whitaker
84a54ca083 uhci: use multiple TDs for data transfers larger than the max packet size. 
Unlike the other USB controllers, a UHCI transfer descriptor can only
request a single packet.
 2022-04-11 21:17:09 +01:00
Martin Whitaker
ae2c010610 uhci: fix device speed setting when constructing a transfer descriptor. 2022-04-10 11:53:01 +01:00
Martin Whitaker
4c55182cd0 Disable UHCI legacy support and make sure all UHCI registers are initialised. 
The controller reset should set the USBINTR, FRNUM, and SOF registers to
their default values, but set them explicitly just to be sure.
 2022-04-09 22:42:59 +01:00
Martin Whitaker
4761b782dd Enable detection of keyboards attached to a UHCI controller. 2022-04-07 18:05:45 +01:00
Martin Whitaker
08bbac1065 uhci: reset the queue head after handling a keyboard interrupt. 
When an interrupt transfer completes, the UHCI loads the QELP in the
QH with the link pointer from the TD (which is a null pointer in this
case). We need to set the QELP back to point at the TD to enable the
next interrupt transfer.
 2022-04-07 17:51:27 +01:00
Martin Whitaker
75bc6822f8 uhci: set the link pointer terminate bit in the last TD in a queue. 2022-04-07 17:43:39 +01:00
Martin Whitaker
6cfb7e7e83 Miscellaneous fixes to the UHCI driver. 
This gets us to the point that a keyboard is detected when running
QEMU with a EHCI/UHCI combination controller and the first keypress
is detected and returned.
 2022-04-07 00:31:59 +02:00
Sam Demeulemeester
43302bf193 Add SPD decoding for DDR memory modules 2022-04-06 23:55:38 +02:00
Martin Whitaker
2c33aa3e85 Check for correct address space in probe_usb_controller() (issue #36). 
We expect UHCI controllers to be mapped into I/O space and the other
controller types to be mapped into Memory space. Print a diagnostic
message and abort if this is not the case. Only call map_region()
for controllers mapped into Memory space.
 2022-04-06 20:46:08 +01:00
Martin Whitaker
711596edbb Add boot command line option to ignore any EHCI controllers. 2022-04-04 22:53:39 +01:00
Sam Demeulemeester
2e048a7c61
Add support for Serial/TTY (#32) 
* Add preliminary support for TTY Serial/UART (#15)

* Use shadow_buffer instead of VGA buffer to get a framebuffer-agnostic TTY supprot

* Added menu browsing & inputs from Serial TTY (#15)

* Add fix for degree symbol on TTY. Correct serial.c & serial.h file created with CRLF (#15)

* Move tty_error_redraw() to insure correct redraw when a error occurs

* Many reindent / cleanup

* Various optimization from @martinwhitaker comments
 2022-04-04 18:31:54 +02:00
Lionel Debroux
5cc72a6bed
Fix up the SMBIOS parser so that it doesn't perform all kinds of OOB accesses when dealing with invalid input. (#26) 2022-04-02 15:43:46 +02:00
Martin Whitaker
95c49848c8 Use the PRC status bit to detect when an XHCI port reset is complete (issue #31). 
Some controllers do not set the PR status bit immediately after it's written,
so polling that to detect when the reset is complete is unsafe.
 2022-04-02 09:28:34 +01:00
Martin Whitaker
bbfaf10240 Revert "Correct the minimum recovery time needed to reset the XHCI port (#31)" 
This reverts commit a95c554c6b.
 2022-04-02 09:21:30 +01:00
Sam Demeulemeester
a95c554c6b Correct the minimum recovery time needed to reset the XHCI port (#31) 2022-04-01 22:06:01 +02:00
Sam Demeulemeester
ee80684c4f Separate benchmark from smbus/smbios and add a separate flag to enable/disable it 2022-04-01 20:34:52 +02:00
Sam Demeulemeester
4a20637f8e Add support for AMD Cezanne APU (Ryzen 5000G) #21 2022-04-01 18:55:43 +02:00
Sam Demeulemeester
d356a7e3f0 Parse MADT table header with the correct struct (#29) 2022-04-01 13:46:04 +02:00
Martin Whitaker
c13bb30893 Fix mapping of MADT (issue #29) 
We need to pass the physical address of the MADT to parse_madt(), not the
virtual address of the table signature, because parse_madt() needs to call
map_region() again to ensure the full table is mapped into virtual memory.
 2022-04-01 10:22:25 +01:00
Lionel Debroux
e0d42db07c Optimize the code by declaring several functions static in system/ehci.c. 
`size memtest_shared` indicates that this saves 200- (x86) / 200+ (x86_64) bytes, but alignment hides the gain.
 2022-03-30 11:54:56 +02:00
Sam Demeulemeester
b6e2a2ace8 Attempt to fix another issue related to #19 by adding a BENCH_MIN_START_ADR constant to force bench location > 16MB in all cases. Correct mem_test_len by adding a x2 multiplier (len=src+dst) 2022-03-29 00:42:34 +02:00
Sam Demeulemeester
a4f1ba37b3 Add support for AMD Ryzen FCH (#21) 2022-03-27 23:47:57 +02:00
Sam Demeulemeester
f7ae4dd395 Add support for Zhaoxin ZX-E & KX CPUs 2022-03-25 20:14:16 +01:00
Sam Demeulemeester
88017f007f Add preliminary support for XMP3 on DDR5 (#23). Fix an issue with wrong SPD values on DDR5 ES modules 2022-03-25 00:33:42 +01:00
Sam Demeulemeester
aaa2061aec Fix an issue with DDR5 capacity detection 2022-03-24 21:49:56 +01:00
Sam Demeulemeester
b22c032b5a Add support for DDR5 in smbus.c. Major rework of various related functions (#2) 2022-03-24 21:49:56 +01:00
Sam Demeulemeester
8e35753ce8 Fix attempt for benchmark memory allocation (#19) 2022-03-24 21:49:56 +01:00
Sam Demeulemeester
b4bab4f829 Add decoding of DMI structure 17 as helper for SPD decoding. Move DMI display function to disaply.h 2022-03-24 21:49:56 +01:00
Sam Demeulemeester
fa206bb865 Added DDR2 SPD decoding (#2) 2022-03-24 21:49:56 +01:00
Sam Demeulemeester
ec1a880288 Reset methods re-ordering (proven more universal for BIOS/UEFI as an attempt to solve #17) 2022-03-24 21:49:56 +01:00
Sam Demeulemeester
bd5e6f3c6b Bring back the cache & memory benchmark feature (preliminary) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
6e57ffec34 Added a lot of modern IMC from Intel's BDW (5th gen) to RPL (13th gen) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
eaf1cbeebb Minor cosmectic changes on smbus.c & Added Amazon JEP106 per AWS team request 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
04c3c485a1 Minor fixes on previously added temperature code 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
f9690813ca New code base for SMBUS / SPD access (#2) - WIP 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
de55c0428c Readd hwctrl.h & add argument for reset type 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
2266151fe6 Early SMBUS functions (#2) & EFI Reset (#17) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
b12186b0aa Code cleanup & reindent on smbios.c (#1) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
63904403b2 Added preliminary BIOS/EFI SMBIOS table parsing & basic printing (#1) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
300fd7c1cf Add temperature display for AMD Zen CPU (#3) 2022-03-24 21:49:56 +01:00
Martin Whitaker
0873e3b60a Include string.h, not memory.h, when using memcpy and memset. 
memory.h is an anachronism, and not present on all systems.
 2022-03-11 18:07:01 +00:00
Sam DEMEULEMEESTER
4bc3b6a3c8 Add additional reset method 2022-03-08 23:30:31 +01:00
Sam DEMEULEMEESTER
09f5525f33 Add additional reset method 2022-03-08 23:24:25 +01:00
Martin Whitaker
b609c4dd81 Make detection of EHCI asynchronous transfer complete more robust. 
Using Interrupt On Completion is not robust, because the interrupt flag
is also set if a short transfer is detected. So we need to poll the
Active flag in the transfer descriptors.
 2022-03-06 18:20:53 +00:00
Martin Whitaker
5e2ab9289b Make sure the XHCI private memory is accessible. 
The XHCI device index and scratchpad buffers are mapped into high memory,
in order to conserve low memory. They need to be accessible in the virtual
address space to allow us to initialise them. After initialisation. only
the XHCI accesses them.

We also only need to access the data structures in the device private
workspace during initialisation, but keeping separate physical and virtual
addresses for these structures makes the code considerably more complex,
so for now, move these to low memory.
 2022-03-05 16:27:24 +00:00