Commit Graph

14 Commits

Author SHA1 Message Date
Sam Demeulemeester
03a5222ee2 Add support for Zen4/AM5 DDR5 SPD 2022-09-09 18:09:13 +02:00
Sam Demeulemeester
a5576974cf Add ACPI Timer as the primary TSC correction source and PIT Timer as fallback 2022-06-19 16:39:03 +02:00
Sam Demeulemeester
6cd356f831 Add External L2 detection for ALi Aladdin V Chipset (#87) 2022-06-06 19:56:04 +02:00
martinwhitaker
93c9c8ded5
Rework memory mapping to allow for larger program size (#54)
* Improve abstraction in vmem.h and limit memory benchmarking to first 2GB.

The third GB may get used for remapping memory regions that are only
accessed during startup, so it's not safe to use it for the memory
speed tests.

* Fix calculation of end limit for locating memory benchmark workspace.

* Document vmem.h.

* Use window number, not current start address, to detect first window.

* Increase the program low-load range from 1MB to 4MB and make more robust.

If the BIOS has reserved some parts of low memory, there may not be
enough contiguous space left to load the program there (issue #49).
So increase the low-load range to include the first 3MB of high
memory. Also guard against the program being initially loaded
straddling the new boundary.

Co-authored-by: Martin Whitaker <memtest@martin-whitaker.me.uk>
2022-04-28 23:04:01 +02:00
Sam Demeulemeester
ee80684c4f Separate benchmark from smbus/smbios and add a separate flag to enable/disable it 2022-04-01 20:34:52 +02:00
Sam Demeulemeester
4a20637f8e Add support for AMD Cezanne APU (Ryzen 5000G) #21 2022-04-01 18:55:43 +02:00
Sam Demeulemeester
b6e2a2ace8 Attempt to fix another issue related to #19 by adding a BENCH_MIN_START_ADR constant to force bench location > 16MB in all cases. Correct mem_test_len by adding a x2 multiplier (len=src+dst) 2022-03-29 00:42:34 +02:00
Sam Demeulemeester
f7ae4dd395 Add support for Zhaoxin ZX-E & KX CPUs 2022-03-25 20:14:16 +01:00
Sam Demeulemeester
8e35753ce8 Fix attempt for benchmark memory allocation (#19) 2022-03-24 21:49:56 +01:00
Sam Demeulemeester
bd5e6f3c6b Bring back the cache & memory benchmark feature (preliminary) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
6e57ffec34 Added a lot of modern IMC from Intel's BDW (5th gen) to RPL (13th gen) 2022-03-24 21:49:56 +01:00
Sam DEMEULEMEESTER
300fd7c1cf Add temperature display for AMD Zen CPU (#3) 2022-03-24 21:49:56 +01:00
Martin Whitaker
16d55b7dad Remove distinction between physical and virtual CPUs.
This is no longer needed, now we can display as many CPUs as we can
physically handle.
2022-01-31 22:59:14 +00:00
Martin Whitaker
fbd3376668 Initial commit. 2020-05-24 21:30:55 +01:00