memtest86plus/lib/spinlock.h
Chao Li 97922cc4cf
Add LoongArch support (#410)
* lib/assert: Add LoongArch assert support

Added LoongArch break 3 assert instruction.

Signed-off-by: Chao Li <lichao@loongson.cn>

* lib/barrier: Add barrier method for LoongArch

Added LoongArch barriers in barrier_spin_wait and barrier_halt_wait
functions.

Signed-off-by: Chao Li <lichao@loognson.cn>

* lib/spinlock: Add LoongArch CPU pause

Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.

Signed-off-by: Chao Li <lichao@loongson.cn>

* lib/string: Make LoongArch use the string function in the file

Since LoongArch GCC doesn't have built-in string functions, use the
string function instance in the sting.c

Signed-off-by: Chao Li <lichao@loongson.cn>

* lib/unistd: Add LoongArch CPU pause

Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/acpi: Reduce the way of search RSDP for non-x86 ARCHs

Searching RSDP from legacy BIOS EDBA and reserved areas is available
only on i386 and x64.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/cache: Add LoongArch64 cache operations support

Added cache operations support for LoongArch64.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/cpuid: Add the compile limit

Make the `cpuid` function action only on i386/x64.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/heap: Add heap support for LoongArch64

LoongArch64 uses the low 256MB as the low memory.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/memrw: Add 8-bit and 16-bit memory operations

Added 8-bit and 16-bit memory access operations, which 8-bit uses
`movb` and 16-bit is `movw`.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/memrw: Add LoongArch memory access operations

Added 8/16/32/64-bit memory access operations for LoongArch64.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system: Add Loongson PCI vendor ID and Loongson 7A chipset EHCI workaround

1. Added Loongson PCI vendor ID.
2. Added Loongson 7A chipset ECHI workaround.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/io: Add LoongArch64 IO port operations

Added IO port operations for LoongArch64.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/reloc64: Add LoongArch64 relocations support

Added R_LARCH_RELATIVE and R_LARCH_NONE relocations support for
LoongArch64.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/serial: Add Loongson CPU serial port support

Add the serial port address perfix of Loongson CPU and obtain serial
port clock method.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/smbus: Rename smbus.c to i2c_x86.c

Renamed the smbus.c to i2c_x86.c in i386 and x64 platforms.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/smp: Add LoongArch SMP support

Added LoongArch multi-core support and a way of map to node numbers if
the NUMA is enabled.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/timers: Add LoongArch supports

In LoongArch, there is a stable counter that is independent of other
clocks, it like the TSC in x64. Using it to count the ticks per
millisecond.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/tsc: Add LoongArch support

Usually the frequency of stable counter is not same to CPU frequency, so
using the performance counter for the delay operations.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/usbhcd: Add LoongArch MMIO perfix

Added LoongArch64 MMIO address perfix, use for address the PCI memory
space.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/usbhcd: Add Loongson 7A2000 chipset OHCI BAR offset fix

If the BAR address is not fixed for the Loongson 7A2000 OHCI controller,
some prots will not be usable, This change currently only affects the
LoongArch platform.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system: Add the way to IO access via MMIO

Usually, it is access the IO like PCI IO via MMIO on non-X86 ARCHs, so
a method to access IO via MMIO is added.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system: Add the way to access PCI memory space via MMIO

Some uniformly address ARCHs access the PCI memory depended the MMIO, so
the method to access PCI memory via MMIO is added.

Signed-off-by: Chao Li <lichao@loongson.cn>

* app: Add LoongArch version support

Reduced the version field by two characters to support ARCH name
abbreviations with more than three characters, and added "la64" ARCH
version display.

Singed-off-by: Chao Li <lichao@loongson.cn>

* test/block_move: Add block move test via ASM for LoongArch

Add block move test inline assembly instance for LoongArch.

Signed-off-by: Chao Li <lichao@loongson.cn>

* test/mov_inv_fixed: Add LoongArch ASM version word write operation

Add LoongArch ASM version word write cycle if it uses the HAND_OPTIMISED.

Signed-off-by: Chao Li <lichao@loongson.cn>

* boot: Adjust the AP stack size for LoongArch

LoongArch exception will store all of the GP, FP and CSR on stack, it
need more stack size, make LoongArch AP using 2KB stack size.

Signed-off-by: Chao Li <lichao@loongson.cn>

* boot/efisetup: Add LoongArch CPU halt instruction

Add "idle 0" for LoongArch

Signed-off-by: Chao Li <lichao@loongson.cn>

* boot/efi: Limiting the ms_abi using scope

Make the ms_abi only work on i386 and x64.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/imc/loongson: Add Loongson LoongArch IMC support

Added the Loongson LoongArch CPU IMC instance, support read out the IMC
sequence, currently only supports reading MC0.

Signed-off-by: Chao Li <lichao@loongson.cn>

* app/loongarch: Add intrrupt handler for LoongArch

Added the LoongArch IRQ handler support.

Signed-off-by: Chao Li <lichao@loongson.cn>

* system/loongarch: Add LoongArch ARCH specific files

Added LoongArch ARCH specific files: cpuid.c, cpuinfo.c, hwctrl.c,
memctrl.c, temperature.c, vmem.c, registers.h

They use the same pubilc API for i386 and x64 platforms.

Signed-off-by: Chao Li <lichao@loongson.cn>

* boot: Add LoongArch startup and header

Added the header.S and startup64.S for LoongArch, CPU works on:
1. Page mode.
2. Load and store is cacheable.
3. Instructions is cacheable.
4. DMWn 0 and 1 is used.
5. To access non-cacheable areas, use the perfix 0x8000000000000000.

Signed-off Chao Li <lichao@loongson.cn>

* build64/la64: Add LoongArch64 build files

Add infrastructure files to build memtest86 plus for LoongArch64
platform.

Signed-off-by: Chao Li <lichao@loongson.cn>

* workflows: Add LoongArch64 CI supports

Adjust workflow logci, remvoe 32 and 64 wordsize, replace with "i386,
x86_64 and la64", add LoongArch64 build CI check.

Signed-off-by: Chao Li <lichao@loongson.cn>

---------

Signed-off-by: Chao Li <lichao@loongson.cn>
Signed-off-by: Chao Li <lichao@loognson.cn>
2024-08-30 13:38:46 +02:00

85 lines
1.5 KiB
C

// SPDX-License-Identifier: GPL-2.0
#ifndef SPINLOCK_H
#define SPINLOCK_H
/**
* \file
*
* Provides a lightweight mutex synchronisation primitive.
*
*//*
* Copyright (C) 2020-2022 Martin Whitaker.
*/
#include <stdbool.h>
/**
* A mutex object. Use spin_unlock() to initialise prior to first use.
*/
typedef volatile bool spinlock_t;
#ifdef __loongarch_lp64
/**
* LoongArch CPU pause.
*/
static inline void cpu_pause (void)
{
__asm__ __volatile__ (
"nop \n\t" \
"nop \n\t" \
"nop \n\t" \
"nop \n\t" \
"nop \n\t" \
"nop \n\t" \
"nop \n\t" \
"nop \n\t" \
);
}
#endif
/**
* Spins until the mutex is unlocked.
*/
static inline void spin_wait(spinlock_t *lock)
{
if (lock) {
while (*lock) {
#if defined(__x86_64) || defined(__i386__)
__builtin_ia32_pause();
#elif defined (__loongarch_lp64)
cpu_pause();
#endif
}
}
}
/**
* Spins until the mutex is unlocked, then locks the mutex.
*/
static inline void spin_lock(spinlock_t *lock)
{
if (lock) {
while (!__sync_bool_compare_and_swap(lock, false, true)) {
do {
#if defined(__x86_64) || defined(__i386__)
__builtin_ia32_pause();
#elif defined (__loongarch_lp64)
cpu_pause();
#endif
} while (*lock);
}
}
}
/**
* Unlocks the mutex.
*/
static inline void spin_unlock(spinlock_t *lock)
{
if (lock) {
__sync_synchronize();
*lock = false;
}
}
#endif // SPINLOCK_H