mirror of
https://github.com/memtest86plus/memtest86plus.git
synced 2024-11-23 08:26:23 -06:00
22663f89bb
Add various quirks to handle AMD temp sensors erratas
230 lines
6.1 KiB
C
230 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef CPUID_H
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#define CPUID_H
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/**
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* \file
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*
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* Provides access to the CPUID information.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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* Copyright (C) 2004-2022 Sam Demeulemeester.
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*
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* Derived from memtest86+ cpuid.h
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*/
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#include <stdint.h>
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#define CPU_ECORE_ID 0x20
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#define CPU_PCORE_ID 0x40
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typedef enum {
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CORE_UNKNOWN,
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CORE_PCORE,
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CORE_ECORE
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} core_type_t;
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/**
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* Structures that hold the collected CPUID information.
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*/
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typedef union {
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uint32_t raw[2];
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struct {
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uint32_t stepping : 4;
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uint32_t model : 4;
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uint32_t family : 4;
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uint32_t processorType : 2;
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uint32_t : 2;
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uint32_t extendedModel : 4;
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uint32_t extendedFamily : 8;
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uint32_t : 4;
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uint32_t extendedBrandID : 32; // AMD Only
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};
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} cpuid_version_t;
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typedef union {
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uint32_t raw;
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struct {
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uint32_t brandIndex : 8;
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uint32_t cflushLineSize : 8;
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uint32_t logicalProcessorCount : 8;
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uint32_t apicID : 8;
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};
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} cpuid_proc_info_t;
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typedef union {
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uint32_t raw[3];
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struct {
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uint32_t fpu : 1; // EDX feature flags, bit 0 */
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uint32_t vme : 1;
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uint32_t de : 1;
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uint32_t pse : 1;
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uint32_t rdtsc : 1;
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uint32_t msr : 1;
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uint32_t pae : 1;
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uint32_t mce : 1;
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uint32_t cx8 : 1;
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uint32_t apic : 1;
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uint32_t : 1;
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uint32_t sep : 1;
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uint32_t mtrr : 1;
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uint32_t pge : 1;
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uint32_t mca : 1;
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uint32_t cmov : 1;
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uint32_t pat : 1;
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uint32_t pse36 : 1;
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uint32_t psn : 1;
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uint32_t cflush : 1;
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uint32_t : 1;
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uint32_t ds : 1;
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uint32_t acpi : 1;
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uint32_t mmx : 1;
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uint32_t fxsr : 1;
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uint32_t sse : 1;
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uint32_t sse2 : 1;
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uint32_t ss : 1;
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uint32_t htt : 1;
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uint32_t tm : 1;
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uint32_t bit30 : 1;
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uint32_t pbe : 1; // EDX feature flags, bit 31
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uint32_t sse3 : 1; // ECX feature flags, bit 0
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uint32_t mulq : 1;
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uint32_t bit2 : 1;
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uint32_t mon : 1;
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uint32_t dscpl : 1;
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uint32_t vmx : 1;
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uint32_t smx : 1;
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uint32_t eist : 1;
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uint32_t tm2 : 1;
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uint32_t : 12; // ECX feature flags, bit 20
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uint32_t x2apic : 1;
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uint32_t : 10; // ECX feature flags, bit 31
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uint32_t : 29; // EDX extended feature flags, bit 0
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uint32_t lm : 1;
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uint32_t : 2; // EDX extended feature flags, bit 31
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};
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} cpuid_feature_flags_t;
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#define CPUID_VENDOR_LENGTH 3
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#define CPUID_VENDOR_STR_LENGTH (CPUID_VENDOR_LENGTH * sizeof(uint32_t) + 1) // includes space for null terminator
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typedef union {
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uint32_t raw[CPUID_VENDOR_LENGTH];
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char str[CPUID_VENDOR_STR_LENGTH];
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} cpuid_vendor_string_t;
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#define CPUID_BRAND_LENGTH 12
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#define CPUID_BRAND_STR_LENGTH (CPUID_BRAND_LENGTH * sizeof(uint32_t) + 1) // includes space for null terminator
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typedef union {
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uint32_t raw[CPUID_BRAND_LENGTH];
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char str[CPUID_BRAND_STR_LENGTH];
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} cpuid_brand_string_t;
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typedef union {
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uint32_t raw[4];
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struct {
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uint32_t : 24;
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uint32_t l1_i_size : 8;
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uint32_t : 24;
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uint32_t l1_d_size : 8;
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uint32_t : 16;
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uint32_t l2_size : 16;
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uint32_t : 18;
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uint32_t l3_size : 14;
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};
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} cpuid_cache_info_t;
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typedef union {
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uint32_t raw;
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struct {
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uint32_t : 1;
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};
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} cpuid_custom_features;
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typedef struct {
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int core_count;
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int thread_count;
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int is_hybrid;
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int ecore_count;
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int pcore_count;
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} cpuid_topology_t;
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typedef struct {
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uint32_t max_cpuid;
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uint32_t max_xcpuid;
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uint32_t dts_pmp;
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cpuid_version_t version;
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cpuid_proc_info_t proc_info;
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cpuid_feature_flags_t flags;
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cpuid_vendor_string_t vendor_id;
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cpuid_brand_string_t brand_id;
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cpuid_cache_info_t cache_info;
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cpuid_custom_features custom;
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cpuid_topology_t topology;
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} cpuid_info_t;
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typedef union {
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uint32_t raw;
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struct {
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uint32_t ctype : 5;
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uint32_t level : 3;
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uint32_t is_self_initializing : 1;
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uint32_t is_fully_associative : 1;
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uint32_t reserved : 4;
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uint32_t num_threads_sharing : 12;
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uint32_t num_cores_on_die : 6;
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};
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} cpuid4_eax_t;
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typedef union {
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uint32_t raw;
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struct {
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uint32_t coherency_line_size : 12;
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uint32_t physical_line_partition : 10;
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uint32_t ways_of_associativity : 10;
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};
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} cpuid4_ebx_t;
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typedef union {
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uint32_t raw;
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struct {
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uint32_t number_of_sets : 32;
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};
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} cpuid4_ecx_t;
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/**
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* The CPUID information collected by cpuid_init();
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*/
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extern cpuid_info_t cpuid_info;
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/**
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* Reads the CPUID information and stores it in cpuid_info.
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*/
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void cpuid_init(void);
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/**
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* Return the Core Type (for Hybrid CPUs)
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*/
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core_type_t get_ap_hybrid_type(void);
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/**
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* Executes the cpuid instruction.
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*/
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static inline void cpuid(uint32_t op, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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*eax = op;
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*ecx = count;
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__asm__ __volatile__ ("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax),
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"2" (*ecx)
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);
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}
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#endif // CPUID_H
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