mirror of
https://github.com/memtest86plus/memtest86plus.git
synced 2024-11-23 00:16:24 -06:00
97922cc4cf
* lib/assert: Add LoongArch assert support Added LoongArch break 3 assert instruction. Signed-off-by: Chao Li <lichao@loongson.cn> * lib/barrier: Add barrier method for LoongArch Added LoongArch barriers in barrier_spin_wait and barrier_halt_wait functions. Signed-off-by: Chao Li <lichao@loognson.cn> * lib/spinlock: Add LoongArch CPU pause Because the LoongArch haven't pause instruction, using eight nops to replace the pause. Signed-off-by: Chao Li <lichao@loongson.cn> * lib/string: Make LoongArch use the string function in the file Since LoongArch GCC doesn't have built-in string functions, use the string function instance in the sting.c Signed-off-by: Chao Li <lichao@loongson.cn> * lib/unistd: Add LoongArch CPU pause Because the LoongArch haven't pause instruction, using eight nops to replace the pause. Signed-off-by: Chao Li <lichao@loongson.cn> * system/acpi: Reduce the way of search RSDP for non-x86 ARCHs Searching RSDP from legacy BIOS EDBA and reserved areas is available only on i386 and x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/cache: Add LoongArch64 cache operations support Added cache operations support for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/cpuid: Add the compile limit Make the `cpuid` function action only on i386/x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/heap: Add heap support for LoongArch64 LoongArch64 uses the low 256MB as the low memory. Signed-off-by: Chao Li <lichao@loongson.cn> * system/memrw: Add 8-bit and 16-bit memory operations Added 8-bit and 16-bit memory access operations, which 8-bit uses `movb` and 16-bit is `movw`. Signed-off-by: Chao Li <lichao@loongson.cn> * system/memrw: Add LoongArch memory access operations Added 8/16/32/64-bit memory access operations for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add Loongson PCI vendor ID and Loongson 7A chipset EHCI workaround 1. Added Loongson PCI vendor ID. 2. Added Loongson 7A chipset ECHI workaround. Signed-off-by: Chao Li <lichao@loongson.cn> * system/io: Add LoongArch64 IO port operations Added IO port operations for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/reloc64: Add LoongArch64 relocations support Added R_LARCH_RELATIVE and R_LARCH_NONE relocations support for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/serial: Add Loongson CPU serial port support Add the serial port address perfix of Loongson CPU and obtain serial port clock method. Signed-off-by: Chao Li <lichao@loongson.cn> * system/smbus: Rename smbus.c to i2c_x86.c Renamed the smbus.c to i2c_x86.c in i386 and x64 platforms. Signed-off-by: Chao Li <lichao@loongson.cn> * system/smp: Add LoongArch SMP support Added LoongArch multi-core support and a way of map to node numbers if the NUMA is enabled. Signed-off-by: Chao Li <lichao@loongson.cn> * system/timers: Add LoongArch supports In LoongArch, there is a stable counter that is independent of other clocks, it like the TSC in x64. Using it to count the ticks per millisecond. Signed-off-by: Chao Li <lichao@loongson.cn> * system/tsc: Add LoongArch support Usually the frequency of stable counter is not same to CPU frequency, so using the performance counter for the delay operations. Signed-off-by: Chao Li <lichao@loongson.cn> * system/usbhcd: Add LoongArch MMIO perfix Added LoongArch64 MMIO address perfix, use for address the PCI memory space. Signed-off-by: Chao Li <lichao@loongson.cn> * system/usbhcd: Add Loongson 7A2000 chipset OHCI BAR offset fix If the BAR address is not fixed for the Loongson 7A2000 OHCI controller, some prots will not be usable, This change currently only affects the LoongArch platform. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add the way to IO access via MMIO Usually, it is access the IO like PCI IO via MMIO on non-X86 ARCHs, so a method to access IO via MMIO is added. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add the way to access PCI memory space via MMIO Some uniformly address ARCHs access the PCI memory depended the MMIO, so the method to access PCI memory via MMIO is added. Signed-off-by: Chao Li <lichao@loongson.cn> * app: Add LoongArch version support Reduced the version field by two characters to support ARCH name abbreviations with more than three characters, and added "la64" ARCH version display. Singed-off-by: Chao Li <lichao@loongson.cn> * test/block_move: Add block move test via ASM for LoongArch Add block move test inline assembly instance for LoongArch. Signed-off-by: Chao Li <lichao@loongson.cn> * test/mov_inv_fixed: Add LoongArch ASM version word write operation Add LoongArch ASM version word write cycle if it uses the HAND_OPTIMISED. Signed-off-by: Chao Li <lichao@loongson.cn> * boot: Adjust the AP stack size for LoongArch LoongArch exception will store all of the GP, FP and CSR on stack, it need more stack size, make LoongArch AP using 2KB stack size. Signed-off-by: Chao Li <lichao@loongson.cn> * boot/efisetup: Add LoongArch CPU halt instruction Add "idle 0" for LoongArch Signed-off-by: Chao Li <lichao@loongson.cn> * boot/efi: Limiting the ms_abi using scope Make the ms_abi only work on i386 and x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/imc/loongson: Add Loongson LoongArch IMC support Added the Loongson LoongArch CPU IMC instance, support read out the IMC sequence, currently only supports reading MC0. Signed-off-by: Chao Li <lichao@loongson.cn> * app/loongarch: Add intrrupt handler for LoongArch Added the LoongArch IRQ handler support. Signed-off-by: Chao Li <lichao@loongson.cn> * system/loongarch: Add LoongArch ARCH specific files Added LoongArch ARCH specific files: cpuid.c, cpuinfo.c, hwctrl.c, memctrl.c, temperature.c, vmem.c, registers.h They use the same pubilc API for i386 and x64 platforms. Signed-off-by: Chao Li <lichao@loongson.cn> * boot: Add LoongArch startup and header Added the header.S and startup64.S for LoongArch, CPU works on: 1. Page mode. 2. Load and store is cacheable. 3. Instructions is cacheable. 4. DMWn 0 and 1 is used. 5. To access non-cacheable areas, use the perfix 0x8000000000000000. Signed-off Chao Li <lichao@loongson.cn> * build64/la64: Add LoongArch64 build files Add infrastructure files to build memtest86 plus for LoongArch64 platform. Signed-off-by: Chao Li <lichao@loongson.cn> * workflows: Add LoongArch64 CI supports Adjust workflow logci, remvoe 32 and 64 wordsize, replace with "i386, x86_64 and la64", add LoongArch64 build CI check. Signed-off-by: Chao Li <lichao@loongson.cn> --------- Signed-off-by: Chao Li <lichao@loongson.cn> Signed-off-by: Chao Li <lichao@loognson.cn>
187 lines
6.0 KiB
C
187 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2020-2022 Martin Whitaker.
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// Copyright (C) 2024 Loongson Technology Corporation Limited. All rights reserved.
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//
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// Derived from an extract of memtest86+ test.c:
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//
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// MemTest86+ V5 Specific code (GPL V2.0)
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// By Samuel DEMEULEMEESTER, sdemeule@memtest.org
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// http://www.canardpc.com - http://www.memtest.org
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// Thanks to Passmark for calculate_chunk() and various comments !
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// ----------------------------------------------------
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// test.c - MemTest-86 Version 3.4
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//
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// Released under version 2 of the Gnu Public License.
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// By Chris Brady
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#include <stdbool.h>
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#include <stdint.h>
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#include "display.h"
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#include "error.h"
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#include "test.h"
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#include "test_funcs.h"
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#include "test_helper.h"
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#define HAND_OPTIMISED 1 // Use hand-optimised assembler code for performance.
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//------------------------------------------------------------------------------
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// Public Functions
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//------------------------------------------------------------------------------
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int test_mov_inv_fixed(int my_cpu, int iterations, testword_t pattern1, testword_t pattern2)
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{
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int ticks = 0;
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if (my_cpu == master_cpu) {
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display_test_pattern_value(pattern1);
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}
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// Initialize memory with the initial pattern.
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for (int i = 0; i < vm_map_size; i++) {
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testword_t *start, *end;
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calculate_chunk(&start, &end, my_cpu, i, sizeof(testword_t));
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if (end < start) SKIP_RANGE(1) // we need at least one word for this test
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testword_t *p = start;
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testword_t *pe = start;
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bool at_end = false;
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do {
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// take care to avoid pointer overflow
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if ((end - pe) >= SPIN_SIZE) {
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pe += SPIN_SIZE - 1;
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} else {
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at_end = true;
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pe = end;
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}
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ticks++;
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if (my_cpu < 0) {
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continue;
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}
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test_addr[my_cpu] = (uintptr_t)p;
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#if HAND_OPTIMISED
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#if defined(__x86_64__)
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uint64_t length = pe - p + 1;
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__asm__ __volatile__ ("\t"
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"rep \n\t"
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"stosq \n\t"
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:
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: "c" (length), "D" (p), "a" (pattern1)
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:
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);
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p = pe;
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#elif defined(__i386__)
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uint32_t length = pe - p + 1;
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__asm__ __volatile__ ("\t"
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"rep \n\t"
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"stosl \n\t"
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:
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: "c" (length), "D" (p), "a" (pattern1)
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:
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);
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p = pe;
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#elif defined(__loongarch_lp64)
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uint64_t length = pe - p + 1;
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__asm__ __volatile__ ("\t"
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"loop: \n\t"
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"st.d %2, %1, 0x0 \n\t"
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"addi.d %1, %1, 0x8 \n\t"
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"addi.d %0, %0, -0x1 \n\t"
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"bnez %0, loop \n\t"
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:
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: "r" (length), "r" (p), "r" (pattern1)
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: "memory"
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);
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p = pe;
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#endif
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#else
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do {
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write_word(p, pattern1);
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} while (p++ < pe); // test before increment in case pointer overflows
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#endif
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do_tick(my_cpu);
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BAILOUT;
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} while (!at_end && ++pe); // advance pe to next start point
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}
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// Check for the current pattern and then write the alternate pattern for
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// each memory location. Test from the bottom up and then from the top down.
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for (int i = 0; i < iterations; i++) {
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flush_caches(my_cpu);
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for (int j = 0; j < vm_map_size; j++) {
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testword_t *start, *end;
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calculate_chunk(&start, &end, my_cpu, j, sizeof(testword_t));
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if (end < start) SKIP_RANGE(1) // we need at least one word for this test
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testword_t *p = start;
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testword_t *pe = start;
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bool at_end = false;
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do {
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// take care to avoid pointer overflow
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if ((end - pe) >= SPIN_SIZE) {
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pe += SPIN_SIZE - 1;
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} else {
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at_end = true;
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pe = end;
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}
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ticks++;
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if (my_cpu < 0) {
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continue;
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}
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test_addr[my_cpu] = (uintptr_t)p;
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do {
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testword_t actual = read_word(p);
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if (unlikely(actual != pattern1)) {
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data_error(p, pattern1, actual, true);
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}
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write_word(p, pattern2);
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} while (p++ < pe); // test before increment in case pointer overflows
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do_tick(my_cpu);
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BAILOUT;
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} while (!at_end && ++pe); // advance pe to next start point
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}
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flush_caches(my_cpu);
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for (int j = vm_map_size - 1; j >= 0; j--) {
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testword_t *start, *end;
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calculate_chunk(&start, &end, my_cpu, j, sizeof(testword_t));
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if (end < start) SKIP_RANGE(1) // we need at least one word for this test
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testword_t *p = end;
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testword_t *ps = end;
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bool at_start = false;
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do {
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// take care to avoid pointer underflow
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if ((ps - start) >= SPIN_SIZE) {
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ps -= SPIN_SIZE - 1;
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} else {
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at_start = true;
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ps = start;
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}
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ticks++;
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if (my_cpu < 0) {
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continue;
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}
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test_addr[my_cpu] = (uintptr_t)p;
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do {
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testword_t actual = read_word(p);
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if (unlikely(actual != pattern2)) {
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data_error(p, pattern2, actual, true);
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}
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write_word(p, pattern1);
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} while (p-- > ps); // test before decrement in case pointer overflows
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do_tick(my_cpu);
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BAILOUT;
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} while (!at_start && --ps); // advance ps to next start point
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}
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}
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return ticks;
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}
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