mirror of
https://github.com/memtest86plus/memtest86plus.git
synced 2024-11-23 08:26:23 -06:00
97922cc4cf
* lib/assert: Add LoongArch assert support Added LoongArch break 3 assert instruction. Signed-off-by: Chao Li <lichao@loongson.cn> * lib/barrier: Add barrier method for LoongArch Added LoongArch barriers in barrier_spin_wait and barrier_halt_wait functions. Signed-off-by: Chao Li <lichao@loognson.cn> * lib/spinlock: Add LoongArch CPU pause Because the LoongArch haven't pause instruction, using eight nops to replace the pause. Signed-off-by: Chao Li <lichao@loongson.cn> * lib/string: Make LoongArch use the string function in the file Since LoongArch GCC doesn't have built-in string functions, use the string function instance in the sting.c Signed-off-by: Chao Li <lichao@loongson.cn> * lib/unistd: Add LoongArch CPU pause Because the LoongArch haven't pause instruction, using eight nops to replace the pause. Signed-off-by: Chao Li <lichao@loongson.cn> * system/acpi: Reduce the way of search RSDP for non-x86 ARCHs Searching RSDP from legacy BIOS EDBA and reserved areas is available only on i386 and x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/cache: Add LoongArch64 cache operations support Added cache operations support for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/cpuid: Add the compile limit Make the `cpuid` function action only on i386/x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/heap: Add heap support for LoongArch64 LoongArch64 uses the low 256MB as the low memory. Signed-off-by: Chao Li <lichao@loongson.cn> * system/memrw: Add 8-bit and 16-bit memory operations Added 8-bit and 16-bit memory access operations, which 8-bit uses `movb` and 16-bit is `movw`. Signed-off-by: Chao Li <lichao@loongson.cn> * system/memrw: Add LoongArch memory access operations Added 8/16/32/64-bit memory access operations for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add Loongson PCI vendor ID and Loongson 7A chipset EHCI workaround 1. Added Loongson PCI vendor ID. 2. Added Loongson 7A chipset ECHI workaround. Signed-off-by: Chao Li <lichao@loongson.cn> * system/io: Add LoongArch64 IO port operations Added IO port operations for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/reloc64: Add LoongArch64 relocations support Added R_LARCH_RELATIVE and R_LARCH_NONE relocations support for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/serial: Add Loongson CPU serial port support Add the serial port address perfix of Loongson CPU and obtain serial port clock method. Signed-off-by: Chao Li <lichao@loongson.cn> * system/smbus: Rename smbus.c to i2c_x86.c Renamed the smbus.c to i2c_x86.c in i386 and x64 platforms. Signed-off-by: Chao Li <lichao@loongson.cn> * system/smp: Add LoongArch SMP support Added LoongArch multi-core support and a way of map to node numbers if the NUMA is enabled. Signed-off-by: Chao Li <lichao@loongson.cn> * system/timers: Add LoongArch supports In LoongArch, there is a stable counter that is independent of other clocks, it like the TSC in x64. Using it to count the ticks per millisecond. Signed-off-by: Chao Li <lichao@loongson.cn> * system/tsc: Add LoongArch support Usually the frequency of stable counter is not same to CPU frequency, so using the performance counter for the delay operations. Signed-off-by: Chao Li <lichao@loongson.cn> * system/usbhcd: Add LoongArch MMIO perfix Added LoongArch64 MMIO address perfix, use for address the PCI memory space. Signed-off-by: Chao Li <lichao@loongson.cn> * system/usbhcd: Add Loongson 7A2000 chipset OHCI BAR offset fix If the BAR address is not fixed for the Loongson 7A2000 OHCI controller, some prots will not be usable, This change currently only affects the LoongArch platform. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add the way to IO access via MMIO Usually, it is access the IO like PCI IO via MMIO on non-X86 ARCHs, so a method to access IO via MMIO is added. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add the way to access PCI memory space via MMIO Some uniformly address ARCHs access the PCI memory depended the MMIO, so the method to access PCI memory via MMIO is added. Signed-off-by: Chao Li <lichao@loongson.cn> * app: Add LoongArch version support Reduced the version field by two characters to support ARCH name abbreviations with more than three characters, and added "la64" ARCH version display. Singed-off-by: Chao Li <lichao@loongson.cn> * test/block_move: Add block move test via ASM for LoongArch Add block move test inline assembly instance for LoongArch. Signed-off-by: Chao Li <lichao@loongson.cn> * test/mov_inv_fixed: Add LoongArch ASM version word write operation Add LoongArch ASM version word write cycle if it uses the HAND_OPTIMISED. Signed-off-by: Chao Li <lichao@loongson.cn> * boot: Adjust the AP stack size for LoongArch LoongArch exception will store all of the GP, FP and CSR on stack, it need more stack size, make LoongArch AP using 2KB stack size. Signed-off-by: Chao Li <lichao@loongson.cn> * boot/efisetup: Add LoongArch CPU halt instruction Add "idle 0" for LoongArch Signed-off-by: Chao Li <lichao@loongson.cn> * boot/efi: Limiting the ms_abi using scope Make the ms_abi only work on i386 and x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/imc/loongson: Add Loongson LoongArch IMC support Added the Loongson LoongArch CPU IMC instance, support read out the IMC sequence, currently only supports reading MC0. Signed-off-by: Chao Li <lichao@loongson.cn> * app/loongarch: Add intrrupt handler for LoongArch Added the LoongArch IRQ handler support. Signed-off-by: Chao Li <lichao@loongson.cn> * system/loongarch: Add LoongArch ARCH specific files Added LoongArch ARCH specific files: cpuid.c, cpuinfo.c, hwctrl.c, memctrl.c, temperature.c, vmem.c, registers.h They use the same pubilc API for i386 and x64 platforms. Signed-off-by: Chao Li <lichao@loongson.cn> * boot: Add LoongArch startup and header Added the header.S and startup64.S for LoongArch, CPU works on: 1. Page mode. 2. Load and store is cacheable. 3. Instructions is cacheable. 4. DMWn 0 and 1 is used. 5. To access non-cacheable areas, use the perfix 0x8000000000000000. Signed-off Chao Li <lichao@loongson.cn> * build64/la64: Add LoongArch64 build files Add infrastructure files to build memtest86 plus for LoongArch64 platform. Signed-off-by: Chao Li <lichao@loongson.cn> * workflows: Add LoongArch64 CI supports Adjust workflow logci, remvoe 32 and 64 wordsize, replace with "i386, x86_64 and la64", add LoongArch64 build CI check. Signed-off-by: Chao Li <lichao@loongson.cn> --------- Signed-off-by: Chao Li <lichao@loongson.cn> Signed-off-by: Chao Li <lichao@loognson.cn>
200 lines
5.5 KiB
C
200 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2020-2022 Martin Whitaker.
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//
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// Derived from memtest86+ reloc.c:
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//
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// reloc.c - MemTest-86 Version 3.3
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//
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// Released under version 2 of the Gnu Public License.
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// By Eric Biederman
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#include <stddef.h>
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#include <stdint.h>
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#include "assert.h"
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//------------------------------------------------------------------------------
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// Constants
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//------------------------------------------------------------------------------
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// Dynamic section tag values
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#define DT_NULL 0 // End of dynamic section
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#define DT_PLTRELSZ 2 // Size in bytes of PLT relocs
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#define DT_RELA 7 // Address of Rel relocs
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#define DT_RELASZ 8 // Total size of Rel relocs
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#define DT_RELAENT 9
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#define DT_PLTREL 20 // Type of reloc in PLT
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#define DT_JMPREL 23 // Address of PLT relocs
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#define DT_NUM 34 // Number of tag values
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// Relocation types
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#define R_X86_64_NONE 0
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#define R_X86_64_RELATIVE 8
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#define R_LARCH_NONE 0
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#define R_LARCH_RELATIVE 3
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//------------------------------------------------------------------------------
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// Types
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//------------------------------------------------------------------------------
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typedef uint64_t Elf64_Addr;
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typedef int64_t Elf64_Sxword;
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typedef uint64_t Elf64_Xword;
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typedef struct
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{
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Elf64_Sxword d_tag;
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union
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{
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Elf64_Xword d_val;
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Elf64_Addr d_ptr;
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} d_un;
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} Elf64_Dyn;
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typedef struct
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{
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Elf64_Addr r_offset;
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Elf64_Xword r_info;
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Elf64_Sxword r_addend;
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} Elf64_Rela;
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//------------------------------------------------------------------------------
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// Private Functions
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//------------------------------------------------------------------------------
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#define ELF64_R_TYPE(r_info) ((r_info) & 0xffffffff)
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/*
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* Return the run-time load address of the shared object.
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*/
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static inline Elf64_Addr __attribute__ ((unused)) get_load_address(void)
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{
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Elf64_Addr addr;
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#if defined(__x86_64__)
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__asm__ __volatile__ (
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"leaq _start(%%rip), %0"
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: "=r" (addr)
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:
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: "cc"
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);
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#elif defined(__loongarch_lp64)
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__asm__ __volatile__ (
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"la.pcrel %0, _start"
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: "=r" (addr)
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:
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: "memory"
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);
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#endif
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return addr;
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}
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/*
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* Return the link-time address of _DYNAMIC. Conveniently, this is the first
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* element of the GOT.
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*/
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static inline Elf64_Addr __attribute__ ((unused)) get_dynamic_section_offset(void)
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{
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Elf64_Addr offs;
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#if defined(__x86_64__)
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__asm__ __volatile__ (
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"movq _GLOBAL_OFFSET_TABLE_(%%rip), %0"
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: "=r" (offs)
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:
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: "cc"
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);
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#elif defined(__loongarch_lp64)
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__asm__ __volatile__ (
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"la.pcrel $t0, _GLOBAL_OFFSET_TABLE_ \n\t"
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"ld.d %0, $t0, 0x0"
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: "=r" (offs)
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:
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: "$t0", "memory"
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);
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#endif
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return offs;
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}
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static void get_dynamic_info(Elf64_Dyn *dyn_section, Elf64_Addr load_offs, Elf64_Dyn *dyn_info[DT_NUM])
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{
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Elf64_Dyn *dyn = dyn_section;
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while (dyn->d_tag != DT_NULL) {
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if (dyn->d_tag < DT_NUM) {
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dyn_info[dyn->d_tag] = dyn;
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}
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dyn++;
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}
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if (dyn_info[DT_RELA] != NULL) {
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assert(dyn_info[DT_RELAENT]->d_un.d_val == sizeof(Elf64_Rela));
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dyn_info[DT_RELA]->d_un.d_ptr += load_offs;
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}
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if (dyn_info[DT_PLTREL] != NULL) {
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assert(dyn_info[DT_PLTREL]->d_un.d_val == DT_RELA);
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}
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if (dyn_info[DT_JMPREL] != NULL) {
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dyn_info[DT_JMPREL]->d_un.d_ptr += load_offs;
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}
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}
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static void do_relocation(Elf64_Addr load_addr, Elf64_Addr load_offs, const Elf64_Rela *rel)
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{
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Elf64_Addr *target_addr = (Elf64_Addr *)(load_addr + rel->r_offset);
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if ((ELF64_R_TYPE(rel->r_info) == R_X86_64_RELATIVE) ||
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(ELF64_R_TYPE(rel->r_info) == R_LARCH_RELATIVE)) {
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if (load_offs == load_addr) {
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*target_addr = load_addr + rel->r_addend;
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} else {
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*target_addr += load_offs;
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}
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return;
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}
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if ((ELF64_R_TYPE(rel->r_info) == R_X86_64_NONE) ||
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(ELF64_R_TYPE(rel->r_info) == R_LARCH_NONE)) {
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return;
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}
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assert(! "unexpected dynamic reloc type");
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}
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static void do_relocations(Elf64_Addr load_addr, Elf64_Addr load_offs, Elf64_Addr rel_addr, Elf64_Addr rel_size)
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{
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const Elf64_Rela *rel_start = (const Elf64_Rela *)(rel_addr);
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const Elf64_Rela *rel_end = (const Elf64_Rela *)(rel_addr + rel_size);
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for (const Elf64_Rela *rel = rel_start; rel < rel_end; rel++) {
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do_relocation(load_addr, load_offs, rel);
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}
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}
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//------------------------------------------------------------------------------
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// Public Functions
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//------------------------------------------------------------------------------
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void reloc(void)
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{
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static volatile Elf64_Addr last_load_addr = 0;
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Elf64_Dyn *dyn_info[DT_NUM];
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for (int i = 0; i < DT_NUM; i++) {
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dyn_info[i] = NULL;
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}
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Elf64_Addr load_addr = get_load_address();
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Elf64_Addr load_offs = load_addr - last_load_addr;
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if (load_addr == last_load_addr) {
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return;
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}
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last_load_addr = load_addr;
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Elf64_Dyn *dyn_section = (Elf64_Dyn *)(load_addr + get_dynamic_section_offset());
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get_dynamic_info(dyn_section, load_offs, dyn_info);
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do_relocations(load_addr, load_offs, dyn_info[DT_RELA]->d_un.d_ptr, dyn_info[DT_RELASZ]->d_un.d_val);
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if (dyn_info[DT_PLTREL]->d_un.d_val == DT_RELA) {
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do_relocations(load_addr, load_offs, dyn_info[DT_JMPREL]->d_un.d_ptr, dyn_info[DT_PLTRELSZ]->d_un.d_val);
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}
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}
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