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https://github.com/memtest86plus/memtest86plus.git
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f34a85ce07
* Add CPUID detection for MTL & ARL CPUs * Add support for ARL SMBus Controler Add PCI Device polling on Bus 0x80 (instead of fixed 0x00) Solve issue with DDR5 SPD Bank switching when SPD Write is disabled (using Proc Call) * Add Live Freq/Timings IMC Polling for Intel MTL & ADL CPUs * Correct K8 Rev G detection Fix #361 (PR hijacking)
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
#ifndef _SMBUS_H_
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#define _SMBUS_H_
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/**
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* SPDX-License-Identifier: GPL-2.0
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*
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* \file
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*
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* Provides functions for reading SPD via SMBUS
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*
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* Copyright (C) 2004-2023 Sam Demeulemeester.
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*/
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define SPD5_MR11 11
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/* i801 Hosts Addresses */
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#define SMBHSTSTS smbusbase
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#define SMBHSTCNT smbusbase + 2
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#define SMBHSTCMD smbusbase + 3
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#define SMBHSTADD smbusbase + 4
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#define SMBHSTDAT0 smbusbase + 5
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#define SMBHSTDAT1 smbusbase + 6
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#define SMBBLKDAT smbusbase + 7
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#define SMBPEC smbusbase + 8
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#define SMBAUXSTS smbusbase + 12
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#define SMBAUXCTL smbusbase + 13
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/* i801 Hosts Status register bits */
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#define SMBHSTSTS_BYTE_DONE 0x80
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#define SMBHSTSTS_INUSE_STS 0x40
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#define SMBHSTSTS_SMBALERT_STS 0x20
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#define SMBHSTSTS_FAILED 0x10
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#define SMBHSTSTS_BUS_ERR 0x08
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#define SMBHSTSTS_DEV_ERR 0x04
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#define SMBHSTSTS_INTR 0x02
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#define SMBHSTSTS_HOST_BUSY 0x01
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/* i801 Hosts Control register bits */
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#define SMBHSTCNT_QUICK 0x00
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#define SMBHSTCNT_BYTE 0x04
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#define SMBHSTCNT_BYTE_DATA 0x08
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#define SMBHSTCNT_WORD_DATA 0x0C
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#define SMBHSTCNT_PROC_CALL 0x10
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#define SMBHSTCNT_BLOCK_DATA 0x14
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#define SMBHSTCNT_I2C_BLOCK_DATA 0x18
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#define SMBHSTCNT_LAST_BYTE 0x20
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#define SMBHSTCNT_START 0x40
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/* AMD-Specific constants */
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#define AMD_INDEX_IO_PORT 0xCD6
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#define AMD_DATA_IO_PORT 0xCD7
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#define AMD_SMBUS_BASE_REG 0x2C
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#define AMD_PM_INDEX 0x00
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/* nVidia-Specific constants */
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#define NV_SMBUS_ADR_REG 0x20
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#define NV_OLD_SMBUS_ADR_REG 0x50
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#define NVSMBCNT smbusbase + 0
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#define NVSMBSTS smbusbase + 1
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#define NVSMBADD smbusbase + 2
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#define NVSMBCMD smbusbase + 3
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#define NVSMBDAT(x) (smbusbase + 4 + (x))
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#define NVSMBCNT_WRITE 0x00
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#define NVSMBCNT_READ 0x01
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#define NVSMBCNT_QUICK 0x02
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#define NVSMBCNT_BYTE 0x04
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#define NVSMBCNT_BYTE_DATA 0x06
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#define NVSMBCNT_WORD_DATA 0x08
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#define NVSMBSTS_DONE 0x80
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#define NVSMBSTS_ALRM 0x40
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#define NVSMBSTS_RES 0x20
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#define NVSMBSTS_STATUS 0x1f
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/* ALi-Specific constants (M1563 & newer) */
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#define ALI_SMBHSTCNT_SIZEMASK 0x03
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#define ALI_SMBHSTSTS_BAD 0x1C
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#define ALI_SMBHSTCNT_QUICK 0x00
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#define ALI_SMBHSTCNT_BYTE 0x01
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#define ALI_SMBHSTCNT_BYTE_DATA 0x02
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#define ALI_SMBHSTCNT_WORD_DATA 0x03
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#define ALI_SMBHSTCNT_KILL 0x04
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#define ALI_SMBHSTCNT_BLOCK 0x05
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/* ALi-Specific constants (M1543 & older) */
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#define ALI_OLD_SMBHSTSTS_BAD 0xE0
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#define ALI_OLD_SMBHSTSTS_BUSY 0x08
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#define ALI_OLD_SMBHSTCNT_BYTE_DATA 0x20
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#define ALI_OLD_SMBHSTCNT smbusbase + 1
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#define ALI_OLD_SMBHSTSTART smbusbase + 2
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#define ALI_OLD_SMBHSTADD smbusbase + 3
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#define ALI_OLD_SMBHSTDAT0 smbusbase + 4
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#define ALI_OLD_SMBHSTCMD smbusbase + 7
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#define PIIX4_SMB_BASE_ADR_DEFAULT 0x90
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#define PIIX4_SMB_BASE_ADR_VIAPRO 0xD0
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#define PIIX4_SMB_BASE_ADR_ALI1563 0x80
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#define PIIX4_SMB_BASE_ADR_ALI1543 0x14
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struct pci_smbus_controller {
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unsigned vendor;
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unsigned device;
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void (*get_adr)(void);
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};
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/**
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* Print SPD Info
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*/
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void print_spd_startup_info(void);
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uint8_t get_spd(uint8_t slot_idx, uint16_t spd_adr);
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#endif // SMBUS_H
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