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84 lines
2.1 KiB
C
84 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef PCI_H
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#define PCI_H
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/**
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* \file
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*
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* Provides functions to perform PCI configuration space reads and writes.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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*/
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#include <stdint.h>
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#define PCI_MAX_BUS 256
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#define PCI_MAX_DEV 32
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#define PCI_MAX_FUNC 8
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/**
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* Initialises the PCI access support.
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*/
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void pci_init(void);
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/**
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* Returns an 8 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space.
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*/
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uint8_t pci_config_read8(int bus, int dev, int func, int reg);
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/**
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* Returns a 16 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space. The address must be 16-bit
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* aligned.
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*/
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uint16_t pci_config_read16(int bus, int dev, int func, int reg);
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/**
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* Returns a 32 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space. The address must be 32-bit
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* aligned.
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*/
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uint32_t pci_config_read32(int bus, int dev, int func, int reg);
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/**
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* Writes an 8 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space.
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*/
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void pci_config_write8(int bus, int dev, int func, int reg, uint8_t value);
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/**
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* Writes a 16 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space. The address must be 16-bit aligned.
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*/
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void pci_config_write16(int bus, int dev, int func, int reg, uint16_t value);
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/**
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* Writes a 32 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space. The address must be 32-bit aligned.
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*/
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void pci_config_write32(int bus, int dev, int func, int reg, uint32_t value);
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/**
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* Basic LPC Functions
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*/
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void lpc_outb(uint8_t cmd, uint8_t data);
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uint8_t lpc_inb(uint8_t reg);
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/*
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* Add some SNM related function (S.DEMEULEMEESTER)
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*/
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#define SMN_SMUIO_THM 0x00059800
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#define SMN_THM_TCON_CUR_TMP (SMN_SMUIO_THM + 0x00)
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/**
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* Read & Write to AMD Family 17h SNM
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*/
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uint32_t amd_smn_read(uint32_t adr);
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void amd_smn_write(uint32_t adr, uint32_t data);
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#endif // PCI_H
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