mirror of
https://github.com/memtest86plus/memtest86plus.git
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97922cc4cf
* lib/assert: Add LoongArch assert support Added LoongArch break 3 assert instruction. Signed-off-by: Chao Li <lichao@loongson.cn> * lib/barrier: Add barrier method for LoongArch Added LoongArch barriers in barrier_spin_wait and barrier_halt_wait functions. Signed-off-by: Chao Li <lichao@loognson.cn> * lib/spinlock: Add LoongArch CPU pause Because the LoongArch haven't pause instruction, using eight nops to replace the pause. Signed-off-by: Chao Li <lichao@loongson.cn> * lib/string: Make LoongArch use the string function in the file Since LoongArch GCC doesn't have built-in string functions, use the string function instance in the sting.c Signed-off-by: Chao Li <lichao@loongson.cn> * lib/unistd: Add LoongArch CPU pause Because the LoongArch haven't pause instruction, using eight nops to replace the pause. Signed-off-by: Chao Li <lichao@loongson.cn> * system/acpi: Reduce the way of search RSDP for non-x86 ARCHs Searching RSDP from legacy BIOS EDBA and reserved areas is available only on i386 and x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/cache: Add LoongArch64 cache operations support Added cache operations support for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/cpuid: Add the compile limit Make the `cpuid` function action only on i386/x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/heap: Add heap support for LoongArch64 LoongArch64 uses the low 256MB as the low memory. Signed-off-by: Chao Li <lichao@loongson.cn> * system/memrw: Add 8-bit and 16-bit memory operations Added 8-bit and 16-bit memory access operations, which 8-bit uses `movb` and 16-bit is `movw`. Signed-off-by: Chao Li <lichao@loongson.cn> * system/memrw: Add LoongArch memory access operations Added 8/16/32/64-bit memory access operations for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add Loongson PCI vendor ID and Loongson 7A chipset EHCI workaround 1. Added Loongson PCI vendor ID. 2. Added Loongson 7A chipset ECHI workaround. Signed-off-by: Chao Li <lichao@loongson.cn> * system/io: Add LoongArch64 IO port operations Added IO port operations for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/reloc64: Add LoongArch64 relocations support Added R_LARCH_RELATIVE and R_LARCH_NONE relocations support for LoongArch64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/serial: Add Loongson CPU serial port support Add the serial port address perfix of Loongson CPU and obtain serial port clock method. Signed-off-by: Chao Li <lichao@loongson.cn> * system/smbus: Rename smbus.c to i2c_x86.c Renamed the smbus.c to i2c_x86.c in i386 and x64 platforms. Signed-off-by: Chao Li <lichao@loongson.cn> * system/smp: Add LoongArch SMP support Added LoongArch multi-core support and a way of map to node numbers if the NUMA is enabled. Signed-off-by: Chao Li <lichao@loongson.cn> * system/timers: Add LoongArch supports In LoongArch, there is a stable counter that is independent of other clocks, it like the TSC in x64. Using it to count the ticks per millisecond. Signed-off-by: Chao Li <lichao@loongson.cn> * system/tsc: Add LoongArch support Usually the frequency of stable counter is not same to CPU frequency, so using the performance counter for the delay operations. Signed-off-by: Chao Li <lichao@loongson.cn> * system/usbhcd: Add LoongArch MMIO perfix Added LoongArch64 MMIO address perfix, use for address the PCI memory space. Signed-off-by: Chao Li <lichao@loongson.cn> * system/usbhcd: Add Loongson 7A2000 chipset OHCI BAR offset fix If the BAR address is not fixed for the Loongson 7A2000 OHCI controller, some prots will not be usable, This change currently only affects the LoongArch platform. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add the way to IO access via MMIO Usually, it is access the IO like PCI IO via MMIO on non-X86 ARCHs, so a method to access IO via MMIO is added. Signed-off-by: Chao Li <lichao@loongson.cn> * system: Add the way to access PCI memory space via MMIO Some uniformly address ARCHs access the PCI memory depended the MMIO, so the method to access PCI memory via MMIO is added. Signed-off-by: Chao Li <lichao@loongson.cn> * app: Add LoongArch version support Reduced the version field by two characters to support ARCH name abbreviations with more than three characters, and added "la64" ARCH version display. Singed-off-by: Chao Li <lichao@loongson.cn> * test/block_move: Add block move test via ASM for LoongArch Add block move test inline assembly instance for LoongArch. Signed-off-by: Chao Li <lichao@loongson.cn> * test/mov_inv_fixed: Add LoongArch ASM version word write operation Add LoongArch ASM version word write cycle if it uses the HAND_OPTIMISED. Signed-off-by: Chao Li <lichao@loongson.cn> * boot: Adjust the AP stack size for LoongArch LoongArch exception will store all of the GP, FP and CSR on stack, it need more stack size, make LoongArch AP using 2KB stack size. Signed-off-by: Chao Li <lichao@loongson.cn> * boot/efisetup: Add LoongArch CPU halt instruction Add "idle 0" for LoongArch Signed-off-by: Chao Li <lichao@loongson.cn> * boot/efi: Limiting the ms_abi using scope Make the ms_abi only work on i386 and x64. Signed-off-by: Chao Li <lichao@loongson.cn> * system/imc/loongson: Add Loongson LoongArch IMC support Added the Loongson LoongArch CPU IMC instance, support read out the IMC sequence, currently only supports reading MC0. Signed-off-by: Chao Li <lichao@loongson.cn> * app/loongarch: Add intrrupt handler for LoongArch Added the LoongArch IRQ handler support. Signed-off-by: Chao Li <lichao@loongson.cn> * system/loongarch: Add LoongArch ARCH specific files Added LoongArch ARCH specific files: cpuid.c, cpuinfo.c, hwctrl.c, memctrl.c, temperature.c, vmem.c, registers.h They use the same pubilc API for i386 and x64 platforms. Signed-off-by: Chao Li <lichao@loongson.cn> * boot: Add LoongArch startup and header Added the header.S and startup64.S for LoongArch, CPU works on: 1. Page mode. 2. Load and store is cacheable. 3. Instructions is cacheable. 4. DMWn 0 and 1 is used. 5. To access non-cacheable areas, use the perfix 0x8000000000000000. Signed-off Chao Li <lichao@loongson.cn> * build64/la64: Add LoongArch64 build files Add infrastructure files to build memtest86 plus for LoongArch64 platform. Signed-off-by: Chao Li <lichao@loongson.cn> * workflows: Add LoongArch64 CI supports Adjust workflow logci, remvoe 32 and 64 wordsize, replace with "i386, x86_64 and la64", add LoongArch64 build CI check. Signed-off-by: Chao Li <lichao@loongson.cn> --------- Signed-off-by: Chao Li <lichao@loongson.cn> Signed-off-by: Chao Li <lichao@loognson.cn>
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef BOOT_H
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#define BOOT_H
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/**
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* \file
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*
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* Provides definitions used in the boot code. Also defines exported symbols
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* needed in the main code.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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*/
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/*
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* NOTE: Increasing the value of MAX_APS would require:
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* - relocating the stacks when the program is loaded in low memory
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* - modifying smp.c to support the x2APIC architecture
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* - adjusting the display if more than 3 digits are needed for CPU IDs
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*/
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#define MAX_APS 255 /* Maximum number of active APs */
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#define BSP_STACK_SIZE 16384 /* Stack size for the BSP */
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#ifdef __loongarch_lp64
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#define AP_STACK_SIZE 2048 /* Stack size for each AP */
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#else
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#define AP_STACK_SIZE 1024 /* Stack size for each AP */
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#endif
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#define STACKS_SIZE (BSP_STACK_SIZE + MAX_APS * AP_STACK_SIZE)
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#define LOCALS_SIZE 16 /* Stack region reserved for thread-local storage */
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#define LOW_LOAD_ADDR 0x00010000 /* The low load address for the main program */
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#define HIGH_LOAD_ADDR 0x00100000 /* The high load address for the main program */
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#define SETUP_SECS 2 /* Size of the 16-bit setup code in sectors */
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#define BOOT_SEG 0x07c0 /* Segment address for the 16-bit boot code */
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#define SETUP_SEG 0x07e0 /* Segment address for the 16-bit setup code */
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#define MAIN_SEG 0x1000 /* Segment address for the main program code
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when loaded by the 16-bit bootloader */
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#define KERNEL_CS 0x10 /* 32-bit segment address for code */
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#define KERNEL_DS 0x18 /* 32-bit segment address for data */
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/* The following addresses are offsets from BOOT_SEG. */
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#define BOOT_STACK ((1 + SETUP_SECS) * 512)
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#define BOOT_STACK_TOP ((MAIN_SEG - BOOT_SEG) << 4)
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/* The following definitions must match the Linux boot_params struct. */
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#define E820_ENTRIES 0x1e8 /* offsetof(boot_params.e820_entries) */
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#define E820_MAP 0x2d0 /* offsetof(boot_params.e820_table) */
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#define E820_MAP_SIZE 128 /* max. number of entries in E820_MAP */
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/* The following definitions must match the Linux e820_entry struct. */
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#define E820_ADDR 0 /* offsetof(e820_entry.addr) */
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#define E820_SIZE 8 /* offsetof(e820_entry.size) */
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#define E820_TYPE 16 /* offsetof(e820_entry.type) */
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#define E820_ENTRY_SIZE 20 /* sizeof(e820_entry) */
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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extern uint8_t _start[];
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extern uint8_t startup32[];
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extern uint8_t startup64[];
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extern uint8_t startup[];
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extern uint64_t pml4[];
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extern uint64_t pdp[];
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extern uint64_t pd0[];
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extern uint64_t pd1[];
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extern uint64_t pd2[];
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extern uint64_t pd3[];
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extern uintptr_t boot_params_addr;
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extern uint8_t ap_trampoline[];
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extern uint32_t ap_startup_addr;
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extern uint8_t ap_trampoline_end[];
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extern uint8_t _stacks[];
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extern uint8_t _end[];
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#endif /* ! __ASSEMBLY__ */
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#endif /* BOOT_H */
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