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127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2020-2022 Martin Whitaker.
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//
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// Partly derived from an extract of memtest86+ test.c:
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//
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// MemTest86+ V5 Specific code (GPL V2.0)
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// By Samuel DEMEULEMEESTER, sdemeule@memtest.org
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// http://www.canardpc.com - http://www.memtest.org
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// Thanks to Passmark for calculate_chunk() and various comments !
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// ----------------------------------------------------
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// test.c - MemTest-86 Version 3.4
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//
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// Released under version 2 of the Gnu Public License.
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// By Chris Brady
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#include <stdint.h>
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#include "cache.h"
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#include "smp.h"
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#include "barrier.h"
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#include "config.h"
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#include "display.h"
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#include "test_helper.h"
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//------------------------------------------------------------------------------
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// Types
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//------------------------------------------------------------------------------
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// We keep a separate LFSR for each CPU. Space them out by at least a cache line,
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// otherwise performance suffers.
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typedef struct {
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uint64_t lfsr;
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uint64_t pad[7];
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} prsg_state_t;
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//------------------------------------------------------------------------------
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// Private Variables
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//------------------------------------------------------------------------------
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static prsg_state_t prsg_state[MAX_CPUS];
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//------------------------------------------------------------------------------
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// Private Functions
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//------------------------------------------------------------------------------
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static inline uint32_t prsg(int my_cpu)
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{
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// This implements a 64 bit linear feedback shift register with XNOR
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// feedback from taps 64, 63, 61, 60. It generates 32 new bits each
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// time the function is called. Because the feedback taps are all in
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// the upper 32 bits, we can generate the new bits in parallel.
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uint64_t lfsr = prsg_state[my_cpu].lfsr;
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uint32_t feedback = ~((lfsr >> 32) ^ (lfsr >> 31) ^ (lfsr >> 29) ^ (lfsr >> 28));
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prsg_state[my_cpu].lfsr = (lfsr << 32) | feedback;
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return feedback;
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}
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//------------------------------------------------------------------------------
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// Public Functions
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//------------------------------------------------------------------------------
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void random_seed(int my_cpu, uint64_t seed)
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{
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if (my_cpu < 0) {
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return;
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}
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// Avoid the PRSG illegal state.
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if (~seed == 0) {
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seed = 0;
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}
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prsg_state[my_cpu].lfsr = seed;
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}
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testword_t random(int my_cpu)
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{
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if (my_cpu < 0) {
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return 0;
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}
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testword_t value = prsg(my_cpu);
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#if TESTWORD_WIDTH > 32
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value = value << 32 | prsg(my_cpu);
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#endif
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return value;
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}
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void calculate_chunk(testword_t **start, testword_t **end, int my_cpu, int segment, size_t chunk_align)
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{
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if (my_cpu < 0) {
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my_cpu = 0;
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}
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// If we are only running 1 CPU then test the whole segment.
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if (num_active_cpus == 1) {
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*start = vm_map[segment].start;
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*end = vm_map[segment].end;
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} else {
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uintptr_t segment_size = (vm_map[segment].end - vm_map[segment].start + 1) * sizeof(testword_t);
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uintptr_t chunk_size = round_down(segment_size / num_active_cpus, chunk_align);
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// Calculate chunk boundaries.
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*start = (testword_t *)((uintptr_t)vm_map[segment].start + chunk_size * my_cpu);
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*end = (testword_t *)((uintptr_t)(*start) + chunk_size) - 1;
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if (*end > vm_map[segment].end) {
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*end = vm_map[segment].end;
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}
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}
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}
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void flush_caches(int my_cpu)
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{
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if (my_cpu >= 0) {
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barrier_wait(run_barrier);
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if (my_cpu == master_cpu) {
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cache_flush();
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}
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barrier_wait(run_barrier);
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}
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}
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