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https://github.com/memtest86plus/memtest86plus.git
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03b6cbe4e4
Refactor cpuinfo() for AMD Family 19h CPUs and add detection for AMD Chagall, Storm Peak, Rembrandt, Phoenix and Granite Ridge
133 lines
4.2 KiB
C
133 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef CPUINFO_H
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#define CPUINFO_H
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/**
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* \file
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*
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* Provides information about the CPU type, clock speed and cache sizes.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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* Copyright (C) 2004-2023 Sam Demeulemeester.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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/**
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* IMC Definition
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*/
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#define IMC_NHM 0x1000 // Core i7 1st Gen 45 nm (Nehalem/Bloomfield)
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#define IMC_WMR 0x1010 // Core 1st Gen 32 nm (Westmere)
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#define IMC_SNB 0x1020 // Core 2nd Gen (Sandy Bridge)
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#define IMC_IVB 0x1030 // Core 3rd Gen (Ivy Bridge)
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#define IMC_HSW 0x1040 // Core 4th Gen (Haswell)
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#define IMC_BDW 0x1050 // Core 5th Gen (Broadwell)
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#define IMC_SKL 0x1060 // Core 6th Gen (Sky Lake-S/H/E)
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#define IMC_KBL 0x1070 // Core 7/8/9th Gen (Kaby/Coffee/Comet Lake)
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#define IMC_CNL 0x1080 // Cannon Lake
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#define IMC_RKL 0x1090 // Core 11th Gen (Rocket Lake)
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#define IMC_ADL 0x1100 // Core 12th Gen (Alder Lake-S)
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#define IMC_RPL 0x1110 // Core 13th Gen (Raptor Lake)
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#define IMC_MTL 0x1120 // Core 14th Gen (Meteor Lake)
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#define IMC_NHM_E 0x2010 // Core i7 1st Gen 45 nm (Nehalem-E)
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#define IMC_SNB_E 0x2020 // Core 2nd Gen (Sandy Bridge-E)
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#define IMC_IVB_E 0x2030 // Core 3rd Gen (Ivy Bridge-E)
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#define IMC_HSW_E 0x2040 // Core 3rd Gen (Haswell-E)
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#define IMC_SKL_SP 0x2050 // Skylake/Cascade Lake/Cooper Lake (Server)
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#define IMC_BDW_E 0x2060 // Broadwell-E (Server)
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#define IMC_BDW_DE 0x2070 // Broadwell-DE (Server)
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#define IMC_ICL_SP 0x2080 // Ice Lake-SP/DE (Server)
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#define IMC_SPR 0x2090 // Sapphire Rapids (Server)
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#define IMC_HSW_ULT 0x3010 // Core 4th Gen (Haswell-ULT)
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#define IMC_SKL_UY 0x3020 // Core 6th Gen (Sky Lake-U/Y)
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#define IMC_KBL_UY 0x3030 // Core 7/8/9th Gen (Kaby/Coffee/Comet/Amber Lake-U/Y)
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#define IMC_ICL 0x3040 // Core 10th Gen (IceLake-Y)
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#define IMC_TGL 0x3050 // Core 11th Gen (Tiger Lake-U)
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#define IMC_ADL_N 0x3061 // Core 12th Gen (Alder Lake-N - Gracemont E-Cores only)
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#define IMC_BYT 0x4010 // Atom Bay Trail
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#define IMC_SLT 0x4020 // Atom Silverthorne / Diamondville
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#define IMC_PNV 0x4030 // Atom Pineview
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#define IMC_CLT 0x4040 // Atom Clover Trail / Cloverview
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#define IMC_CDT 0x4050 // Atom Cedar Trail / Cedarview
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#define IMC_TNC 0x4060 // Atom Tunnel Creek / Lincroft
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#define IMC_K8 0x8000 // Old K8
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#define IMC_K10 0x8010 // K10 (Family 10h & 11h)
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#define IMC_K12 0x8020 // A-Series APU (Family 12h)
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#define IMC_K14 0x8030 // C- / E- / Z- Series APU (Family 14h)
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#define IMC_K15 0x8040 // FX Series (Family 15h)
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#define IMC_K16 0x8050 // Kabini & related (Family 16h)
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#define IMC_K17 0x8060 // Zen & Zen2 (Family 17h)
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#define IMC_K18 0x8070 // Hygon (Family 18h)
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#define IMC_K19_VRM 0x8080 // Zen3 (Family 19h - Vermeer)
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#define IMC_K19_CZN 0x8081 // Cezanne APU
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#define IMC_K19_CHL 0x8090 // Zen3 Chagall TR
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#define IMC_K19_RBT 0x8100 // Zen3+ (Rembrandt)
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#define IMC_K19_RPL 0x8110 // Zen4 (Raphael)
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#define IMC_K19_PHX 0x8120 // Zen4 (Phoenix)
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#define IMC_K19_STK 0x81A0 // Zen4 (Storm Peak)
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#define IMC_K19_GRG 0x8150 // Zen5 (Granite Ridge)
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/**
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* A string identifying the CPU make and model.
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*/
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extern const char *cpu_model;
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/**
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* The size of the L1 cache in KB.
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*/
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extern int l1_cache;
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/**
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* The size of the L2 cache in KB.
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*/
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extern int l2_cache;
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/**
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* The size of the L3 cache in KB.
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*/
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extern int l3_cache;
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/**
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* The bandwidth of the L1 cache
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*/
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extern uint32_t l1_cache_speed;
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/**
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* The bandwidth of the L2 cache
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*/
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extern uint32_t l2_cache_speed;
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/**
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* The bandwidth of the L3 cache
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*/
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extern uint32_t l3_cache_speed;
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/**
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* The bandwidth of the RAM
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*/
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extern uint32_t ram_speed;
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/**
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* The TSC clock speed in kHz. Assumed to be the nominal CPU clock speed.
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*/
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extern uint32_t clks_per_msec;
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/**
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* Determines the CPU info and stores it in the exported variables.
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*/
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void cpuinfo_init(void);
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/**
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* Determines the RAM & caches bandwidth and stores it in the exported variables.
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*/
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void membw_init(void);
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#endif // CPUINFO_H
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