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7aeac7271f
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
97 lines
2.5 KiB
C
97 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef PCI_H
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#define PCI_H
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/**
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* \file
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*
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* Provides functions to perform PCI configuration space reads and writes.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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*/
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#include <stdint.h>
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#define PCI_VID_REG 0x00
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#define PCI_DID_REG 0x02
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#define PCI_SUB_VID_REG 0x2C
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#define PCI_SUB_DID_REG 0x2E
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/* Vendor IDs */
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#define PCI_VID_ATI 0x1002
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#define PCI_VID_AMD 0x1022
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#define PCI_VID_SIS 0x1039
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#define PCI_VID_ASUS 0x1043
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#define PCI_VID_EFAR 0x1055
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#define PCI_VID_ALI 0x10B9
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#define PCI_VID_NVIDIA 0x10DE
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#define PCI_VID_VIA 0x1106
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#define PCI_VID_SERVERWORKS 0x1166
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#define PCI_VID_SUPERMICRO 0x15D9
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#define PCI_VID_HYGON 0x1D94
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#define PCI_VID_INTEL 0x8086
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#define PCI_MAX_BUS 256
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#define PCI_MAX_DEV 32
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#define PCI_MAX_FUNC 8
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/**
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* Initialises the PCI access support.
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*/
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void pci_init(void);
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/**
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* Returns an 8 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space.
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*/
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uint8_t pci_config_read8(int bus, int dev, int func, int reg);
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/**
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* Returns a 16 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space. The address must be 16-bit
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* aligned.
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*/
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uint16_t pci_config_read16(int bus, int dev, int func, int reg);
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/**
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* Returns a 32 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space. The address must be 32-bit
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* aligned.
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*/
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uint32_t pci_config_read32(int bus, int dev, int func, int reg);
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/**
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* Writes an 8 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space.
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*/
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void pci_config_write8(int bus, int dev, int func, int reg, uint8_t value);
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/**
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* Writes a 16 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space. The address must be 16-bit aligned.
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*/
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void pci_config_write16(int bus, int dev, int func, int reg, uint16_t value);
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/**
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* Writes a 32 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space. The address must be 32-bit aligned.
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*/
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void pci_config_write32(int bus, int dev, int func, int reg, uint32_t value);
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/**
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* Basic LPC Functions
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*/
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void lpc_outb(uint8_t cmd, uint8_t data);
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uint8_t lpc_inb(uint8_t reg);
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/**
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* Read & Write to AMD SNM
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*/
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uint32_t amd_smn_read(uint32_t adr);
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void amd_smn_write(uint32_t adr, uint32_t data);
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#endif // PCI_H
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