mirror of
https://github.com/memtest86plus/memtest86plus.git
synced 2026-08-26 13:17:12 -05:00
Sam Demeulemeester
4fa58699a9
* First commit to support x2APIC * Keep apio_x2apic bool everywhere to avoid compilation issues on LA64. x2APIC support on LA64 must be checked later (probably different MSRs) * Various fixes - Fix flags in MADT x2APIC (CPU only has ENABLED, not ONLINE - Increased chunk index and related function from 8 to 16-bit - Increase MAX_APS and MAX_APIC_IDS to 512 (need an APs stack size evaluation to be sure we will not overflow)
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef MSR_H
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#define MSR_H
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/**
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* \file
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*
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* Provides access to the CPU machine-specific registers.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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* Copyright (C) 2020-2026 Sam Demeulemeester.
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*/
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#define MSR_PLATFORM_INFO 0xce
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#define MSR_EBC_FREQUENCY_ID 0x2c
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#define MSR_IA32_PLATFORM_ID 0x17
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#define MSR_IA32_APIC_BASE 0x1b
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#define MSR_IA32_EBL_CR_POWERON 0x2a
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#define MSR_IA32_PLATFORM_INFO 0xce
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#define MSR_IA32_MCG_CTL 0x17b
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#define MSR_IA32_PERF_STATUS 0x198
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#define MSR_IA32_THERM_STATUS 0x19c
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#define MSR_IA32_TEMPERATURE_TARGET 0x1a2
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#define MSR_IA32_X2APIC_BASE 0x800
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#define MSR_EFER 0xc0000080
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#define MSR_K7_HWCR 0xc0010015
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#define MSR_K7_VID_STATUS 0xc0010042
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#define MSR_AMD64_NB_CFG 0xc001001f
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#define MSR_AMD64_COFVID_STATUS 0xc0010071
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#define MSR_AMD64_K17_UMC_MCA_CTRL 0xc00020f0
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#define MSR_AMD64_K17_UMC_MCA_STATUS 0xc00020f1
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#define MSR_AMD64_K17_UMC_MCA_ADDR 0xc00020f2
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#define MSR_AMD64_K1A_UMC_MCA_CTRL 0xc0002150
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#define MSR_AMD64_K1A_UMC_MCA_STATUS 0xc0002151
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#define MSR_AMD64_K1A_UMC_MCA_ADDR 0xc0002152
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#define MSR_AMD64_HW_CONF 0xc0010015
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#define MSR_VIA_TEMP_C7 0x1169
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#define MSR_VIA_TEMP_NANO 0x1423
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#define rdmsr(msr, value1, value2) \
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__asm__ __volatile__("rdmsr" \
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: "=a" (value1), \
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"=d" (value2) \
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: "c" (msr) \
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: "edi" \
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)
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#define wrmsr(msr, value1, value2) \
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__asm__ __volatile__("wrmsr" \
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: /* no outputs */ \
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: "c" (msr), \
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"a" (value1), \
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"d" (value2) \
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)
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#endif // MSR_H
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