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https://github.com/memtest86plus/memtest86plus.git
synced 2026-08-04 10:23:17 -05:00
Sam Demeulemeester
eaeaff181b
Two per-CPU streams alternate NT-store bursts of a fresh PRSG sequence with read-verify of the previous round, forcing write-to-read turnarounds and row conflicts; odd rounds insert idle gaps to provoke PMIC load steps. Targets DDR5-era interface faults (link SI, marginal XMP/EXPO training, voltage droop) that on-die ECC cannot correct Moving PRSG vector kernels from mov_inv_rng.C to a shared module in tests/
99 lines
3.9 KiB
C
99 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef VEC_PRSG_H
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#define VEC_PRSG_H
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/**
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* \file
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*
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* Provides vector-wide pseudo-random sequence primitives shared by the
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* memory tests: per-lane xorshift streams filled and checked through the
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* best available SIMD tier, with scalar fallbacks.
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*
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*//*
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* Copyright (C) 2004-2026 Sam Demeulemeester.
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*/
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#include <stdbool.h>
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#include <stddef.h>
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#include "test.h"
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/**
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* Number of test words processed as one vector block. This matches the AVX2
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* register width on 64-bit builds; the SSE2 and scalar kernels process the
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* same block layout in smaller steps, so each tier remains self-consistent.
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*/
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#define VEC_LANES 4
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#define VEC_BYTES (VEC_LANES * sizeof(testword_t))
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/**
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* The per-lane xorshift states of the current vector block. Carried in
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* memory between kernel invocations, so no SIMD state is live across calls
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* to data_error(), do_tick(), or the thread barriers.
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*/
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typedef struct {
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testword_t lane[VEC_LANES];
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} vec_state_t;
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#if defined(__x86_64__)
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/*
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* SIMD kernels (see tests/x86/vec_prsg_*.c). All kernels start from the
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* lane states in *st, leave the updated states back in *st, and end with an
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* sfence so no non-temporal write is left buffered.
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*
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* The fill kernels write nblocks blocks ascending from p, stepping the lane
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* states forwards after each block (unless splat).
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*
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* The scan kernels stop at the first mismatching block and return the number
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* of blocks completed (== nblocks if all matched), leaving the lane states
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* positioned at the failing block so the caller can report and fix it up:
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* - scan_fwd checks nblocks blocks ascending from p against the lane states,
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* writing the complement and stepping forwards after each matching block.
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* - scan_rev checks nblocks blocks descending from q (which points to the
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* highest block), stepping the lane states backwards before each block,
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* comparing with the complement and restoring the original pattern.
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*/
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void vec_fill_sse2(vec_state_t *st, testword_t *p, size_t nblocks, bool splat);
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size_t vec_scan_fwd_sse2(vec_state_t *st, testword_t *p, size_t nblocks, bool splat);
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size_t vec_scan_rev_sse2(vec_state_t *st, testword_t *q, size_t nblocks, bool splat);
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void vec_fill_avx2(vec_state_t *st, testword_t *p, size_t nblocks, bool splat);
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size_t vec_scan_fwd_avx2(vec_state_t *st, testword_t *p, size_t nblocks, bool splat);
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size_t vec_scan_rev_avx2(vec_state_t *st, testword_t *q, size_t nblocks, bool splat);
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#endif
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/**
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* Initialises the lane states from seed. For splat rounds all lanes hold the
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* same value and are never stepped, giving a uniform background pattern.
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*/
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void seed_lanes(vec_state_t *st, testword_t seed, bool splat);
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/**
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* Fills nblocks vector blocks ascending from p with the lane sequences,
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* dispatching to the best SIMD tier (non-temporal stores) or the scalar
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* fallback. The SIMD kernels process at least one block, so nblocks must
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* be greater than zero.
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*/
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void vec_fill(vec_state_t *st, testword_t *p, size_t nblocks, bool splat);
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/**
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* Checks nblocks vector blocks ascending from p against the lane sequences,
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* writing the complement behind itself (non-temporal on the SIMD tiers).
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* Mismatches are reported via data_error(..., use_for_badram) and fixed up.
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* The SIMD kernels process at least one block, so nblocks must be greater
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* than zero.
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*/
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void vec_check_fwd(vec_state_t *st, testword_t *p, size_t nblocks, bool splat, bool use_for_badram);
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/**
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* Checks nblocks vector blocks descending from p against the complement of
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* the lane sequences, stepping the states backwards and restoring the
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* original pattern behind itself (non-temporal on the SIMD tiers).
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* Mismatches are reported via data_error(..., use_for_badram) and fixed up.
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* The SIMD kernels process at least one block, so nblocks must be greater
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* than zero.
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*/
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void vec_check_rev(vec_state_t *st, testword_t *p, size_t nblocks, bool splat, bool use_for_badram);
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#endif // VEC_PRSG_H
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