mirror of
https://github.com/memtest86plus/memtest86plus.git
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Sam Demeulemeester
2350230351
* Add quirks for ICH0-5 (SMbus Unhide) * Minor constant name changes & typo
118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef PCI_H
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#define PCI_H
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/**
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* \file
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*
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* Provides functions to perform PCI configuration space reads and writes.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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* Copyright (C) 2024 Loongson Technology Corporation Limited. All rights reserved.
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*/
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#include <stdint.h>
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#define PCI_MAX_BUS 256
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#define PCI_MAX_DEV 32
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#define PCI_MAX_FUNC 8
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#define PCI_VID_REG 0x00
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#define PCI_DID_REG 0x02
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#define PCI_SUB_VID_REG 0x2C
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#define PCI_SUB_DID_REG 0x2E
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/* Vendor IDs */
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#define PCI_VID_LOONGSON 0x0014
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#define PCI_VID_ATI 0x1002
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#define PCI_VID_AMD 0x1022
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#define PCI_VID_DELL 0x1028
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#define PCI_VID_SIS 0x1039
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#define PCI_VID_HP 0x103C
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#define PCI_VID_ASUS 0x1043
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#define PCI_VID_EFAR 0x1055
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#define PCI_VID_ALI 0x10B9
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#define PCI_VID_NVIDIA 0x10DE
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#define PCI_VID_VIA 0x1106
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#define PCI_VID_SERVERWORKS 0x1166
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#define PCI_VID_SUPERMICRO 0x15D9
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#define PCI_VID_HYGON 0x1D94
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#define PCI_VID_INTEL 0x8086
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/* Intel Southbridge ISA/LPC (Device 0x1F, Function 0x00) DIDs */
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#define PCI_DID_LPC_ICH 0x2410
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#define PCI_DID_LPC_ICH1 0x2420
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#define PCI_DID_LPC_ICH2 0x2440
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#define PCI_DID_LPC_ICH2M 0x244C
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#define PCI_DID_LPC_ICH3 0x2480
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#define PCI_DID_LPC_ICH3M 0x248C
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#define PCI_DID_LPC_ICH4 0x24C0
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#define PCI_DID_LPC_ICH4M 0x24CC
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#define PCI_DID_LPC_ICH5 0x24D0
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#define PCI_DID_LPC_6300ESB 0x25A1
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#define PCI_DID_LPC_ICH5S 0x25A1
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#define PCI_DID_LPC_ICH6 0x2640
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#define PCI_DID_LPC_ICH6M 0x2641
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#define PCI_DID_LPC_ICH7 0x27B8
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#define PCI_DID_LPC_ICH7M 0x27B9
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/**
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* Initialises the PCI access support.
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*/
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void pci_init(void);
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/**
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* Returns an 8 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space.
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*/
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uint8_t pci_config_read8(int bus, int dev, int func, int reg);
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/**
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* Returns a 16 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space. The address must be 16-bit
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* aligned.
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*/
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uint16_t pci_config_read16(int bus, int dev, int func, int reg);
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/**
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* Returns a 32 bit value read from the specified bus+device+function+register
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* address in the PCI configuration address space. The address must be 32-bit
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* aligned.
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*/
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uint32_t pci_config_read32(int bus, int dev, int func, int reg);
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/**
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* Writes an 8 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space.
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*/
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void pci_config_write8(int bus, int dev, int func, int reg, uint8_t value);
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/**
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* Writes a 16 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space. The address must be 16-bit aligned.
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*/
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void pci_config_write16(int bus, int dev, int func, int reg, uint16_t value);
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/**
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* Writes a 32 bit value to the specified bus+device+function+register address
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* in the PCI configuration address space. The address must be 32-bit aligned.
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*/
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void pci_config_write32(int bus, int dev, int func, int reg, uint32_t value);
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/**
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* Basic LPC Functions
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*/
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void lpc_outb(uint8_t cmd, uint8_t data);
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uint8_t lpc_inb(uint8_t reg);
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/**
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* Read & Write to AMD SNM
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*/
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uint32_t amd_smn_read(uint32_t adr);
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void amd_smn_write(uint32_t adr, uint32_t data);
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#endif // PCI_H
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