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7aeac7271f
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2004-2023 Sam Demeulemeester
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//
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// ------------------------
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//
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// Platform-specific code for AMD Zen CPUs
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//
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#include "cpuinfo.h"
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#include "memctrl.h"
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#include "msr.h"
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#include "pci.h"
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#include "imc.h"
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#define AMD_SMN_UMC_BAR 0x050000
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#define AMD_SMN_UMC_CHB_OFFSET 0x100000
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#define AMD_SMN_UMC_DRAM_CONFIG AMD_SMN_UMC_BAR + 0x200
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#define AMD_SMN_UMC_DRAM_TIMINGS1 AMD_SMN_UMC_BAR + 0x204
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#define AMD_SMN_UMC_DRAM_TIMINGS2 AMD_SMN_UMC_BAR + 0x208
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void get_imc_config_amd_zen(void)
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{
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uint32_t smn_reg, offset;
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uint32_t reg_cha, reg_chb;
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imc.tCL_dec = 0;
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// Get Memory Mapped Register Base Address (Enable MMIO if needed)
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reg_cha = amd_smn_read(AMD_SMN_UMC_DRAM_CONFIG) & 0x7F;
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reg_chb = amd_smn_read(AMD_SMN_UMC_DRAM_CONFIG + AMD_SMN_UMC_CHB_OFFSET) & 0x7F;
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offset = reg_cha ? 0x0 : AMD_SMN_UMC_CHB_OFFSET;
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// Populate IMC width
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imc.width = (reg_cha && reg_chb) ? 128 : 64;
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// Get DRAM Frequency
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smn_reg = amd_smn_read(AMD_SMN_UMC_DRAM_CONFIG + offset);
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if (imc.family >= IMC_K19_RPL) {
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imc.type = "DDR5";
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imc.freq = smn_reg & 0xFFFF;
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if ((smn_reg >> 18) & 1) imc.freq *= 2; // GearDown
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} else {
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imc.type = "DDR4";
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smn_reg = amd_smn_read(AMD_SMN_UMC_DRAM_CONFIG + offset) & 0x7F;
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imc.freq = (float)smn_reg * 66.67f;
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}
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if (imc.freq < 200 || imc.freq > 12000) {
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imc.freq = 0;
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return;
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}
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// Get Timings
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smn_reg = amd_smn_read(AMD_SMN_UMC_DRAM_TIMINGS1 + offset);
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// CAS Latency (tCAS)
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imc.tCL = smn_reg & 0x3F;
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// RAS Active to precharge (tRAS)
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imc.tRAS = (smn_reg >> 8) & 0x7F;
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// RAS-To-CAS (tRC)
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imc.tRCD = (smn_reg >> 16) & 0x3F;
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smn_reg = amd_smn_read(AMD_SMN_UMC_DRAM_TIMINGS2 + offset);
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// RAS Precharge (tRP)
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imc.tRP = (smn_reg >> 16) & 0x3F;
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}
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