Dongyan Qian 07d84f4f34 loongarch: Supports 2K2000/3B6000M (#512) ...

* loongarch: adjust 2K/3B6000M DDR rate factor
* loongarch: Supports fewer cache layers than L3

For example: 2K2000 chip does not have L3, but has L2.
If L2Cache is not flushed to memory, it will cause read and write data errors after cache_off.

2025-05-12 13:56:30 +02:00

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loongarch

loongarch: Supports 2K2000/3B6000M (#512)

2025-05-12 13:56:30 +02:00

x86

Make paths more uniform across architectures; adjust the build system and Github workflows accordingly.

2025-02-24 20:25:29 +01:00

imc.h

Add support for Intel MTL & ARL CPUs (#441)

2024-09-30 13:38:13 +02:00