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https://github.com/memtest86plus/memtest86plus.git
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186ef6e913
* For 64-bit images, use the physical address as the test pattern in test 2. This will make it easier to diagnose faults. * Disable test 1 by default (issue #155). Test 2 provides the same test coverage. Test 1 may make it slightly easier to diagnose faults with a 32-bit image, so leave it as an option. * For 32 bit images, use the physical address to generate the offset in test 2. Detecting a stage change and using that to reset the offset counter could fail when the config menu was used to skip to the next test (issue #224).
254 lines
7.3 KiB
C
254 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2020-2022 Martin Whitaker.
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//
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// Derived from an extract of memtest86+ main.c:
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//
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// MemTest86+ V5 Specific code (GPL V2.0)
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// By Samuel DEMEULEMEESTER, sdemeule@memtest.org
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// http://www.canardpc.com - http://www.memtest.org
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// ------------------------------------------------
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// main.c - MemTest-86 Version 3.5
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//
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// Released under version 2 of the Gnu Public License.
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// By Chris Brady
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#include <stdbool.h>
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#include <stdint.h>
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#include "boot.h"
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#include "cache.h"
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#include "cpuid.h"
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#include "memsize.h"
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#include "tsc.h"
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#include "vmem.h"
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#include "barrier.h"
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#include "config.h"
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#include "display.h"
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#include "test.h"
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#include "test_funcs.h"
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#include "test_helper.h"
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#include "tests.h"
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//------------------------------------------------------------------------------
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// Constants
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//------------------------------------------------------------------------------
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#ifndef TRACE_BARRIERS
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#define TRACE_BARRIERS 0
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#endif
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#define MODULO_N 20
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//------------------------------------------------------------------------------
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// Public Variables
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//------------------------------------------------------------------------------
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test_pattern_t test_list[NUM_TEST_PATTERNS] = {
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// ena, cpu, stgs, itrs, errs, description
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{ true, SEQ, 1, 6, 0, "[Address test, walking ones, no cache] "},
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{false, SEQ, 1, 6, 0, "[Address test, own address in window] "},
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{ true, SEQ, 2, 6, 0, "[Address test, own address + window] "},
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{ true, PAR, 1, 6, 0, "[Moving inversions, 1s & 0s] "},
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{ true, PAR, 1, 3, 0, "[Moving inversions, 8 bit pattern] "},
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{ true, PAR, 1, 30, 0, "[Moving inversions, random pattern] "},
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#if TESTWORD_WIDTH > 32
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{ true, PAR, 1, 3, 0, "[Moving inversions, 64 bit pattern] "},
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#else
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{ true, PAR, 1, 3, 0, "[Moving inversions, 32 bit pattern] "},
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#endif
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{ true, PAR, 1, 81, 0, "[Block move] "},
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{ true, PAR, 1, 48, 0, "[Random number sequence] "},
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{ true, PAR, 1, 6, 0, "[Modulo 20, random pattern] "},
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{ true, ONE, 6, 240, 0, "[Bit fade test, 2 patterns] "},
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};
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int ticks_per_pass[NUM_PASS_TYPES];
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int ticks_per_test[NUM_PASS_TYPES][NUM_TEST_PATTERNS];
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//------------------------------------------------------------------------------
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// Public Functions
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//------------------------------------------------------------------------------
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#define BARRIER \
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if (my_cpu >= 0) { \
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if (TRACE_BARRIERS) { \
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trace(my_cpu, "Run barrier wait at %s line %i", __FILE__, __LINE__); \
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} \
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if (power_save < POWER_SAVE_HIGH) { \
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barrier_spin_wait(run_barrier); \
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} else { \
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barrier_halt_wait(run_barrier); \
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} \
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}
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int run_test(int my_cpu, int test, int stage, int iterations)
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{
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if (my_cpu == master_cpu) {
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if (window_num == 0) {
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// First window, so we need to test all selected lower memory.
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vm_map[0].start = first_word_mapping(pm_limit_lower);
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// For USB_WORKAROUND.
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if (vm_map[0].start < (uintptr_t *)0x500) {
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vm_map[0].start = (uintptr_t *)0x500;
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}
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}
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/* Update display of memory segments being tested */
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uintptr_t pb = page_of(vm_map[0].start);
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uintptr_t pe = page_of(vm_map[vm_map_size - 1].end) + 1;
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display_test_addresses(pb << 2, pe << 2, num_pages_to_test << 2);
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}
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BARRIER;
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testword_t prsg_state;
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int ticks = 0;
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switch (test) {
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// Address test, walking ones.
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case 0:
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if (my_cpu >= 0) cache_off();
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ticks += test_addr_walk1(my_cpu);
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if (my_cpu >= 0) cache_on();
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BAILOUT;
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break;
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// Address test, own address in window.
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case 1:
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ticks += test_own_addr1(my_cpu);
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BAILOUT;
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break;
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// Address test, own address + window.
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case 2:
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ticks += test_own_addr2(my_cpu, stage);
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BAILOUT;
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break;
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// Moving inversions, all ones and zeros.
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case 3: {
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testword_t pattern1 = 0;
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testword_t pattern2 = ~pattern1;
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BARRIER;
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ticks += test_mov_inv_fixed(my_cpu, iterations, pattern1, pattern2);
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BAILOUT;
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BARRIER;
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ticks += test_mov_inv_fixed(my_cpu, iterations, pattern2, pattern1);
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BAILOUT;
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} break;
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// Moving inversions, 8 bit walking ones and zeros.
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case 4: {
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#if TESTWORD_WIDTH > 32
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testword_t pattern1 = UINT64_C(0x8080808080808080);
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#else
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testword_t pattern1 = 0x80808080;
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#endif
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for (int i = 0; i < 8; i++) {
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testword_t pattern2 = ~pattern1;
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BARRIER;
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ticks += test_mov_inv_fixed(my_cpu, iterations, pattern1, pattern2);
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BAILOUT;
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BARRIER;
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ticks += test_mov_inv_fixed(my_cpu, iterations, pattern2, pattern1);
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BAILOUT;
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pattern1 >>= 1;
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}
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} break;
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// Moving inversions, fixed random pattern.
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case 5:
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if (cpuid_info.flags.rdtsc) {
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prsg_state = get_tsc();
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} else {
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prsg_state = 1 + pass_num;
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}
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prsg_state *= 0x12345678;
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for (int i = 0; i < iterations; i++) {
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prsg_state = prsg(prsg_state);
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testword_t pattern1 = prsg_state;
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testword_t pattern2 = ~pattern1;
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BARRIER;
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ticks += test_mov_inv_fixed(my_cpu, 2, pattern1, pattern2);
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BAILOUT;
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}
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break;
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// Moving inversions, 32/64 bit shifting pattern.
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case 6:
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for (int offset = 0; offset < TESTWORD_WIDTH; offset++) {
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BARRIER;
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ticks += test_mov_inv_walk1(my_cpu, iterations, offset, false);
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BAILOUT;
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BARRIER;
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ticks += test_mov_inv_walk1(my_cpu, iterations, offset, true);
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BAILOUT;
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}
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break;
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// Block move.
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case 7:
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ticks += test_block_move(my_cpu, iterations);
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BAILOUT;
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break;
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// Moving inversions, fully random patterns.
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case 8:
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for (int i = 0; i < iterations; i++) {
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BARRIER;
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ticks += test_mov_inv_random(my_cpu);
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BAILOUT;
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}
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break;
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// Modulo 20 check, fixed random pattern.
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case 9:
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if (cpuid_info.flags.rdtsc) {
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prsg_state = get_tsc();
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} else {
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prsg_state = 1 + pass_num;
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}
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prsg_state *= 0x87654321;
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for (int i = 0; i < iterations; i++) {
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for (int offset = 0; offset < MODULO_N; offset++) {
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prsg_state = prsg(prsg_state);
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testword_t pattern1 = prsg_state;
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testword_t pattern2 = ~pattern1;
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BARRIER;
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ticks += test_modulo_n(my_cpu, 2, pattern1, pattern2, MODULO_N, offset);
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BAILOUT;
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BARRIER;
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ticks += test_modulo_n(my_cpu, 2, pattern2, pattern1, MODULO_N, offset);
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BAILOUT;
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}
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}
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break;
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// Bit fade test.
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case 10:
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ticks += test_bit_fade(my_cpu, stage, iterations);
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BAILOUT;
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break;
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}
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return ticks;
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}
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