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https://github.com/memtest86plus/memtest86plus.git
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7aeac7271f
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
101 lines
3.0 KiB
C
101 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2004-2023 Sam Demeulemeester
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//
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// ------------------------
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//
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// Platform-specific code for Intel Alder Lake CPUs (ADL-S)
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//
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#include "cpuinfo.h"
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#include "memctrl.h"
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#include "msr.h"
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#include "pci.h"
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#include "vmem.h"
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#include "imc.h"
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#define ADL_MMR_BASE_REG_LOW 0x48
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#define ADL_MMR_BASE_REG_HIGH 0x4C
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#define ADL_MMR_WINDOW_RANGE (1UL << 17)
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#define ADL_MMR_BASE_MASK 0x3FFFFFE0000
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#define ADL_MMR_MC1_OFFSET 0x10000
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#define ADL_MMR_CH1_OFFSET 0x800
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#define ADL_MMR_IC_DECODE 0xD800
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#define ADL_MMR_CH0_DIMM_REG 0xD80C
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#define ADL_MMR_MC0_REG 0xE000
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#define ADL_MMR_ODT_TCL_REG 0xE070
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#define ADL_MMR_MC_INIT_REG 0xE454
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#define ADL_MMR_SA_PERF_REG 0x5918
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#define ADL_MMR_MC_BIOS_REG 0x5E04
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#define ADL_MMR_BLCK_REG 0x5F60
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void get_imc_config_intel_adl(void)
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{
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uint64_t mmio_reg;
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uint32_t cha, chb, offset;
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float bclk;
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uintptr_t *ptr;
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uint32_t *ptr32;
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// Get Memory Mapped Register Base Address (Enable MMIO if needed)
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mmio_reg = pci_config_read32(0, 0, 0, ADL_MMR_BASE_REG_LOW);
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if (!(mmio_reg & 0x1)) {
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pci_config_write32( 0, 0, 0, ADL_MMR_BASE_REG_LOW, mmio_reg | 1);
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mmio_reg = pci_config_read32(0, 0, 0, ADL_MMR_BASE_REG_LOW);
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if (!(mmio_reg & 0x1)) return;
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}
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mmio_reg |= (uint64_t)pci_config_read32(0, 0, 0, ADL_MMR_BASE_REG_HIGH) << 32;
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mmio_reg &= ADL_MMR_BASE_MASK;
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#ifndef __x86_64__
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if (mmio_reg >= (1ULL << 32)) return; // MMIO is outside reachable range (> 32bit)
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#endif
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uintptr_t mchbar_addr = map_region(mmio_reg, ADL_MMR_WINDOW_RANGE, false);
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// Get channel configuration & IMC width
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cha = *(uintptr_t*)(mchbar_addr + ADL_MMR_CH0_DIMM_REG);
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cha = ~cha ? (((cha >> 16) & 0x7F) + (cha & 0x7F)) : 0;
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chb = *(uintptr_t*)(mchbar_addr + ADL_MMR_CH0_DIMM_REG + ADL_MMR_MC1_OFFSET);
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chb = ~chb ? (((chb >> 16) & 0x7F) + (chb & 0x7F)) : 0;
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offset = cha ? 0x0 : ADL_MMR_MC1_OFFSET;
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imc.width = (cha && chb) ? 64 : 128;
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// Get Memory Type (ADL supports DDR4 & DDR5)
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cha = *(uintptr_t*)(mchbar_addr + offset + ADL_MMR_IC_DECODE) & 0x7;
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imc.type = (cha == 1 || cha == 2) ? "DDR5" : "DDR4";
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// Get SoC Base Clock
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ptr = (uintptr_t*)(mchbar_addr + ADL_MMR_BLCK_REG);
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bclk = (*ptr & 0xFFFFFFFF) / 1000.0f;
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// Get Memory Clock (QClk), apply Gear & clock ratio
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ptr = (uintptr_t*)(mchbar_addr + ADL_MMR_SA_PERF_REG);
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imc.freq = ((*ptr >> 2) & 0xFF) * bclk;
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ptr = (uintptr_t*)(mchbar_addr + ADL_MMR_MC_BIOS_REG);
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imc.freq <<= (*ptr >> 12) & 0x3;
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if ((*ptr & 0xF00) == 0) {
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imc.freq *= 133.34f / 100.0f;
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}
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// Get DRAM Timings
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ptr = (uintptr_t*)(mchbar_addr + offset + ADL_MMR_ODT_TCL_REG);
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imc.tCL = (*ptr >> 16) & 0x7F;
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ptr = (uintptr_t*)(mchbar_addr + offset + ADL_MMR_MC0_REG);
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imc.tRP = *ptr & 0xFF;
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ptr32 = (uint32_t*)((uintptr_t)mchbar_addr + offset + ADL_MMR_MC0_REG + 4);
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imc.tRAS = (*ptr32 >> 10) & 0x1FF;
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imc.tRCD = (*ptr32 >> 19) & 0xFF;
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}
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