mirror of
https://github.com/memtest86plus/memtest86plus.git
synced 2026-08-10 04:58:08 -05:00
Sam Demeulemeester
7fc312d5b0
* Initial commit for ARM64 (header.S & startup.S) * Add Aarch64 interrupt handler * Adapt lib/ to Aarch64 * Small ASM addition for AArch64 * Rewrite Aarch64 system/ - cpuid.c/cpuinfo.c for CPU detection (Qualcomm, Apple, Nvidia, etc) - Add ARM Power State Coordination Interface (PSCI) functions - vmem.c for Virtual Memory MAnagement on ARM64 - Various functions placeholders * Add pseudo-TSC correction for Aarch64 * Add pseudo-tsc measurement for Aarch64 * Add Aarch64 if/elif on basic IO/MMIO/MEM RW functions * Add support for Surface 13 / Snapdragon X KB USB Fix an issue with the XHCI.c drivers with packets > 8 bytes * Add MMIO Serial support for ARM64 * Add ARM64 ASM for block_move & mov_inv_fixed. Fix VM start pointer * Add ARM Serial MMIO configuration * Revert previous commit & reintroduce ARM64 cache functions * Add ACPI MCFG Table description & SMP parsing. This requires careful review/testing to avoid BC issues! * Revert previous commmit and reintroduce relocation and heap change for ARM64 * ARM64 does not support CPU PNS. Use DMI type4 parsing instead. Add SMBIOS v3 support (ARM64 does not support v2) * Fix typo in pci.h * Move Aarch64 load-limit computation from main.c to pmem.c * Add .arm64 to version string. Use PMU for clock computation display. Fix D5 Temp NULL not handled * Add Makefile and linker scripts for aarch64. Set cross-compiler from x86 by default * Attempt to add aarch64 to workflow * Remove a remaining internal debug flag * Correct typos * Fix ARM64 SMP freeze assign heap when RAM is one contiguous region, keep it below 3GB for DMA (RPi5), add DSB before SEV to avoid missed barrier wakeups Sync I-cache with D-cache after program relocation to prevent stale instruction fetch * Validate MADT entry lengths to avoid reading past the table (or looping forever) on malformed ACPI tables * aarch64: add NEON kernels for the vector PRSG tests Tests 3 (bus stress) and 5 (moving inversions, random) now dispatch to 128-bit NEON fill/scan instead of scalar. * Fix ARM64 data abort from the per-second DMI check & fix unbounded strstr() * Fix ARM64 data abort when saving results to USB after a relocation * Update README.md with AArch64 (ARM64) support * aarch64: shrink static string tables, harden MCFG/paging Replace pointer-based name tables with inline char arrays (saves ~1.5KB + relocs) alidate MCFG length/bus ranges, and bound pm_map/vm_map fills against overflows * Add NVIDIA & latest Apple ARM SoC to cpuid.c * Fix stale pointers read by the report writer after a program relocation cpu_model gets a static init (creates its reloc record)SPD type becomes an inline char array
38 lines
791 B
C
38 lines
791 B
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef PMEM_H
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#define PMEM_H
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/**
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* \file
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*
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* Provides a description of the system physical memory map.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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*/
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#include <stddef.h>
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#include <stdint.h>
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#define MAX_MEM_SEGMENTS 128 // must be >= E820_MAP_SIZE (boot.h)
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typedef struct {
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uintptr_t start;
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uintptr_t end;
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} pm_map_t;
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extern pm_map_t pm_map[MAX_MEM_SEGMENTS];
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extern int pm_map_size;
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extern size_t num_pm_pages;
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#if defined(__aarch64__)
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// Load limits computed at run time from the start of physical RAM, which may
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// begin well above address 0. Set by pmem_init().
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extern uintptr_t low_load_limit;
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extern uintptr_t high_load_limit;
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#endif
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void pmem_init(void);
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#endif /* PMEM_H */
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