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7aeac7271f
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
25 lines
700 B
C
25 lines
700 B
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2004-2023 Sam Demeulemeester
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#ifndef _IMC_H_
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#define _IMC_H_
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/* Memory configuration Detection for AMD Zen CPUs */
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void get_imc_config_amd_zen(void);
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/* Memory configuration Detection for Intel Sandy Bridge */
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void get_imc_config_intel_snb(void);
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/* Memory configuration Detection for Intel Haswell */
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void get_imc_config_intel_hsw(void);
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/* Memory configuration Detection for Intel Skylake */
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void get_imc_config_intel_skl(void);
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/* Memory configuration Detection for Intel Ice Lake */
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void get_imc_config_intel_icl(void);
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/* Memory configuration Detection for Intel Alder Lake */
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void get_imc_config_intel_adl(void);
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#endif /* _IMC_H_ */
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