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7aeac7271f
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef MSR_H
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#define MSR_H
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/**
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* \file
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*
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* Provides access to the CPU machine-specific registers.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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*/
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#define MSR_PLATFORM_INFO 0xce
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#define MSR_EBC_FREQUENCY_ID 0x2c
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#define MSR_IA32_PLATFORM_ID 0x17
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#define MSR_IA32_APIC_BASE 0x1b
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#define MSR_IA32_EBL_CR_POWERON 0x2a
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#define MSR_IA32_PLATFORM_INFO 0xce
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#define MSR_IA32_MCG_CTL 0x17b
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#define MSR_IA32_PERF_STATUS 0x198
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#define MSR_IA32_THERM_STATUS 0x19c
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#define MSR_IA32_TEMPERATURE_TARGET 0x1a2
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#define MSR_EFER 0xc0000080
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#define MSR_K7_HWCR 0xc0010015
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#define MSR_K7_VID_STATUS 0xc0010042
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#define MSR_AMD64_NB_CFG 0xc001001f
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#define MSR_AMD64_COFVID_STATUS 0xc0010071
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#define MSR_VIA_TEMP_C7 0x1169
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#define MSR_VIA_TEMP_NANO 0x1423
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#define rdmsr(msr, value1, value2) \
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__asm__ __volatile__("rdmsr" \
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: "=a" (value1), \
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"=d" (value2) \
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: "c" (msr) \
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: "edi" \
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)
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#define wrmsr(msr, value1, value2) \
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__asm__ __volatile__("wrmsr" \
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: /* no outputs */ \
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: "c" (msr), \
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"a" (value1), \
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"d" (value2) \
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)
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#endif // MSR_H
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